1. Test apparatus for testing a circuit unit to be tested, comprising:
a) a nominal data production unit for production of a nominal data stream, which can be supplied to the circuit unit to be tested;
b) a comparison device for comparison of an actual data stream (which is emitted from the circuit unit to be tested as a function of the nominal data stream that is supplied) with the nominal data stream;
c) a compression device for compression of an intermediate result signal (which is emitted from a comparison device as a function of the comparison) into a test result signal; and
d) a buffer storage device for temporary storage of the intermediate result signal which is emitted from the comparison device,
e) wherein, the test apparatus further comprises a read unit for reading the intermediate result signal which is temporarily stored in the buffer storage device, wherein the read unit is designed so as to subdivide the intermediate result signal which is temporarily stored in the buffer storage device, into separate result blocks.
2. Apparatus according to claim 1, wherein the compression device for compression of the intermediate result signal which is emitted from the comparison device is designed such that the test result signal comprises 1 bit of information.
3. Apparatus according to claim 1 wherein the compression device has at least one logic circuit which is in the form of an AND function, such that the test result signal indicates fault-free operation of the circuit unit to be tested only when each of the intermediate result signals indicates fault-free operation of the circuit unit to be tested.
4. Apparatus according to claim 1, wherein the test result signal has a length of 1 bit.
5. Apparatus according to claim 1, wherein the actual data stream comprises odd-numbered actual data and even-numbered actual data.
6. Apparatus according to claim 1, wherein the nominal data stream andor the actual data stream havehas a length of 32 bits.
7. Apparatus according to claim 1, wherein the intermediate result signal which is temporarily stored in the buffer storage device has a length of 32 bits.
8. Apparatus according to claim 1, wherein the result blocks which are produced by the read unit and are produced by subdivision of the intermediate result signal which is temporarily stored in the buffer storage device have a length of 8 bits.
9. Method for testing a circuit unit to be tested, in a test apparatus, having the following steps:
a) producing of a nominal data stream by means of a nominal data production unit;
b) supplying of the nominal data stream to the circuit unit to be tested;
c) comparing of an actual data stream (which is emitted from the circuit unit to be tested as a function of the nominal data stream which is supplied) with the nominal data stream by means of a comparison device;
d) compressing of an intermediate result signal (which is emitted from the comparison device as a function of the comparison) into a test result signal, by means of a compression device; and
e) temporary storing of the intermediate result signal which is emitted from the comparison device in a buffer storage device; wherein the method furthermore comprises the following steps:
f) reading of the intermediate result signal which is temporarily stored in the buffer storage device by means of a read unit, wherein
f1) the read unit subdivides the intermediate result signal, which is temporarily stored in the buffer storage device, into separate result blocks, and wherein
f2) the result blocks which are emitted from the read unit are read via an address bus of the circuit unit to be tested.
10. Method according to claim 9, wherein the intermediate result signal which is emitted from the comparison device is compressed in the compression device into 1 bit of information.
11. Method according to claim 9 wherein the compression device carries out a logic AND operation such that the test result signal indicates fault-free operation of the circuit unit to be tested only when each of the intermediate result signals indicates fault-free operation of the circuit unit to be tested.
12. Method according to claim 9, wherein the test result which corresponds to a test in the circuit unit to be tested is emitted as a test result signal with a length of 1 bit via an output line from the compression device.
13. Method according to claim 9, wherein the actual data stream is formed from odd-numbered actual data and even-numbered actual data, and is emitted from the circuit unit to be tested.
14. Method according to claim 9, wherein the nominal data stream andor the actual data stream areis in the form of data streams with a length of 32 bits.
15. Method according to claim 9, wherein the intermediate result signal which is temporarily stored in the buffer storage device is produced as a signal with a length of 32 bits.
16. Method according to claim 9, wherein the result blocks which are produced by the read unit and are produced by subdivision of the intermediate result signal which is temporarily stored in the buffer storage device are in the form of blocks with a length of 8 bits.
17. Method according to claim 9, wherein the result blocks which are emitted from the read unit are read via the address bus of the circuit unit to be tested, as a function of a test mode signal which is supplied to the read unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A building block logic circuit, comprising:
a first input;
a second input;
a third input; and
a logic output, communicatively coupled to the first input and the second input and the third input;
wherein any one of the first input, the second input and the third input is configurable as a control input for selecting a logical function of the logical circuit and the remaining of the first input, the second input and the third input as logic inputs and the control input is communicatively coupled to a camouflage connector.
2. The logic circuit of claim 1, comprising:
a first inverter having a first inverter input coupled to the first input and a first inverter output;
a second inverter having a second inverter input coupled to the second input and a second inverter output;
a third inverter, having a third inverter input coupled to the third input and a third inverter output;
a fourth inverter having a fourth inverter input and an fourth inverter output representing the logic output;
a first device having:
a first device input coupled to the first inverter output;
a first device gate coupled to the second input;
a first device output coupled to the fourth inverter input;
a second device, having:
a second device input coupled to the first inverter output;
a second device gate coupled to the third inverter output;
a second device output coupled to the fourth inverter input;
a third device, having:
a third device input coupled to the second inverter output;
a third device gate coupled to the third inverter output;
a third device output coupled to the fourth inverter input;
a fourth device, having:
a fourth device input coupled to the second inverter output;
a fourth device gate coupled to the control input;
a fourth device output coupled to the fourth inverter input.
3. The logic circuit of claim 2, wherein:
the first device is a P-channel device;
the second device is an N-channel device;
the third device is an P-channel device; and
the fourth device is a N-channel device.
4. The logic circuit of claim 3, wherein the first device, the second device, the third device, and the fourth device are field effect transistors.
5. The logic circuit of claim 1, wherein:
the first input has a logical state of A and the second input has a logical state of B; and
the selectable logic function of the logic circuit is A+B when the third input is a first logical value and is A\xb7 B when the third input is a second logical value.
6. The logic circuit of claim 1, wherein:
the third input has a logical state of C and the second input has a logical state of B; and
the selectable logic function of the logic circuit is B\xb7C when the first input is a first logical value and B+C when the first input is a second logical value.
7. The logic circuit of claim 1, wherein the control input is programmed.
8. The logic circuit of claim 7, wherein the control input is programmed using a camouflaged circuit.
9. The logic circuit of claim 1, wherein:
the logic output has a logical state being a selectable one of a plurality of logical functions of the remaining of the first input, second input and third inputs, the selectable one of the plurality of logical functions determined at least in part according to which of the first input, the second input, and the third input is configured as the control input.
10. A logic circuit, comprising:
a plurality of interconnected logical building block circuits, each building block circuit having an identical circuit layout and each building block circuit comprising:
a first input;
a second input;
a third input; and
a logic output, communicatively coupled to the first input and the second input and the third input;
wherein any one of the first input, the second input and the third input is configurable as a control input for selecting a logical function of the logical circuit and the remaining of the first input, the second input, and the third input as logic inputs.
11. The logic circuit of claim 10, wherein:
the control input is communicatively coupled to a camouflage connector.
12. The logic circuit of claim 10, wherein each of the logical building block circuits comprises:
a first inverter having a first inverter input coupled to the first input and a first inverter output;
a second inverter having a second inverter input coupled to the second input and a second inverter output;
a third inverter, having a third inverter input coupled to the third input and a third inverter output;
a fourth inverter having a fourth inverter input and an fourth inverter output representing the logic output;
a first device having:
a first device input coupled to the first inverter output;
a first device gate coupled to the control input;
a first device output coupled to the fourth inverter input;
a second device, having:
a second device input coupled to the first inverter output;
a second device gate coupled to the third inverter output;
a second device output coupled to the fourth inverter input;
a third device, having:
a third device input coupled to the second inverter output;
a third device gate coupled to the third inverter output;
a third device output coupled to the fourth inverter input;
a fourth device, having:
a fourth device input coupled to the second inverter output;
a fourth device gate coupled to the control input;
a fourth device output coupled to the fourth inverter input.
13. The logic circuit of claim 12, wherein:
each of the first devices are P-channel devices;
each of the second devices are N-channel devices;
each of the third devices are P-channel devices; and
each of the fourth devices are N-channel devices.
14. The logic circuit of claim 13, wherein each of the first devices, the second devices, the third devices, and the fourth devices are field effect transistors.
15. The logic circuit of claim 10, wherein:
the selectable logic function of at least one of the logical building block circuits is A+B when the control input is a first logical value and is A\xb7 B when the building block’s control input is a second logical value, wherein the first input of the at least one of the logical building block circuits has a logical state of A and the second input of the at least one of the selectable building block circuits has a logical state of B.
16. The logic circuit of claim 10, wherein:
the selectable logic function of at least one of the logical building block circuits is B\xb7C when the first input is a first logical value and B+C when the first input is a second logical value, wherein the second input of the at least one of the logical building block circuits has a logical state of B and the third input of the at least one of the selectable building block circuits has a logical state of C.
17. The logic circuit of claim 10, wherein at least a portion of the control inputs are programmed.
18. The logic circuit of claim 17, wherein the programmed control inputs are programmed using camouflaged circuits.
19. The logic circuit of claim 10, wherein:
the logic output of at least one of the plurality of interconnected building blocks has a logical state being a selectable one of a plurality of logical functions of the remaining of the first input, second input and third inputs, the selectable one of the plurality of logical functions determined at least in part according to which of the first input, the second input, and the third input is configured as the control input.