What is claimed is:
1. A method for protecting a circuit from excessive voltage across first and second terminals of said circuit, comprising the steps of:
(1) sensing first and second voltage amplitudes at said first and second terminals, respectively;
(2) generating an interim voltage amplitude;
(3) coupling said interim voltage amplitude to said second terminal when said first voltage amplitude exceeds a first threshold and said second voltage amplitude is below a second threshold, wherein said interim voltage amplitude is less than said second threshold;
(4) de-coupling said interim voltage amplitude from said second terminal when said second voltage amplitude exceeds said second threshold; and
(5) de-coupling said interim voltage amplitude from said second terminal when said first voltage amplitude is below said first threshold.
2. The method according to claim 1, wherein step (2) comprises generating said interim voltage amplitude from said first voltage amplitude.
3. The method according to claim 1, wherein step (2) comprises generating said interim voltage amplitude independent of said first voltage amplitude.
4. The method according to claim 1, wherein a difference between said first voltage amplitude and said interim voltage amplitude is less than a maximum allowable voltage difference across said first and second terminals of said circuit.
5. The method according to claim 1, wherein said circuit is a transistor, said first terminal is a source terminal of said transistor, and said second terminal is a gate terminal of said transistor.
6. The method according to claim 5, wherein said transistor is a PMOS transistor.
7. The method according to claim 5, wherein said transistor is an NMOS transistor.
8. The method according to claim 1, wherein said circuit is a voltage level shifting circuit on a circuit board, said circuit board further including first circuitry that operates at a first set of voltage amplitudes, second circuitry that operates at a second set of voltage amplitudes, and a plurality of power supplies that provide said first and second sets of voltage amplitudes, wherein said voltage level shifting circuit interfaces said first circuitry with said second circuitry and selectively operates at either of said first and second sets of voltage amplitudes, said voltage level shifting circuit including a transistor wherein said first terminal is a source terminal of said transistor and said second terminal is a gate terminal of said transistor, wherein said first and second terminals are selectively coupled one to said plurality of power supplies to receive either of said first and second sets of voltage amplitudes.
9. An interim voltage generator for protecting a circuit from excessive voltage differences across first and second terminals of said circuit when a first voltage amplitude is applied to said first terminal before a second voltage amplitude is applied to said second terminal, comprising:
first and second terminal pads;
a voltage sensor coupled between said first and second terminal pads, said voltage sensor including first and second thresholds;
a switch having a first contact coupled to said second terminal pad and a control input coupled to an output of said voltage sensor;
an interim voltage supply coupled to a second contact of said switch, said interim voltage supply providing an interim voltage amplitude that is below said second threshold;
whereby said voltage sensor senses voltage amplitudes at said first and second terminal pads and controls said switch to couple said interim voltage supply to said second terminal pad when said voltage amplitude at said first terminal pad exceeds said first threshold and said voltage amplitude at said second terminal pad is below said second threshold.
10. The apparatus according to claim 9, wherein said interim voltage supply comprises a voltage source coupled between said first terminal pad and said second contact of said switch.
11. The apparatus according to claim 10, wherein said interim voltage supply comprises a series of diode-connected transistors coupled between said first terminal pad and said second contact of said switch.
12. The apparatus according to claim 9, wherein said interim voltage supply comprises a voltage source not coupled to said first terminal pad.
13. The apparatus according to claim 9, wherein said switch comprises a normally-open switch.
14. The apparatus according to claim 13, wherein said normally-open switch comprises a transistor, wherein said first terminal of said switch comprises a drain terminal of said transistor, said second terminal of said switch comprises a source terminal of said transistor, and said control input of said switch comprises a gate terminal of said transistor.
15. The apparatus according to claim 14, wherein said transistor comprises a PMOS transistor.
16. The apparatus according to claim 14, wherein said transistor comprises an NMOS transistor.
17. The apparatus according to claim 14, wherein said normally-open switch comprises a first PMOS transistor and said voltage sensor comprises:
a second PMOS transistor having a gate terminal coupled to said second terminal, a source terminal coupled to said first terminal, and a drain terminal coupled to a node;
a first NMOS transistor having a gate terminal coupled to said second terminal, a drain terminal coupled to a relatively low voltage potential, and a source terminal coupled to said node; and
a second NMOS transistor having a gate terminal coupled to said node, a drain terminal coupled to said relatively low potential, and a source terminal coupled to said gate terminal of said first PMOS transistor, wherein said second NMOS transistor selectively couples said second NMOS transistor source terminal to one of said relatively low potential and a relatively high potential, under control of said node.
18. The apparatus according to claim 17, wherein said voltage sensor further comprises a voltage reducer coupled between said first terminal and said second PMOS transistor source terminal.
19. The apparatus according to claim 18, wherein said voltage reducer comprises a series of diode-connected transistors.
20. The apparatus according to claim 17, wherein said voltage sensor further comprises:
a third PMOS transistor having a source terminal coupled to said first terminal, a drain terminal coupled to said node, and a gate terminal coupled to said second NMOS transistor source terminal; and
a fourth PMOS transistor having a source terminal coupled to said first terminal, a drain terminal coupled to said second NMOS transistor source terminal, and a gate terminal coupled to said node.
21. The apparatus according to claim 20, wherein said interim voltage supply comprises a second series of diode-connected transistors coupled between said first terminal and said first PMOS transistor source terminal.
22. The apparatus according to claim 9, further comprising means for limiting DC leakage current between said first and second terminal pads.
23. The apparatus according to claim 6, wherein said circuit is a voltage level shifting circuit on a circuit board, said circuit board further including first circuitry that operates at a first set of voltage amplitudes, second circuitry that operates at a second set of voltage amplitudes, and a plurality of power supplies that provide said first and second sets of voltage amplitudes, wherein said voltage level shifting circuit interfaces said first circuitry with said second circuitry and selectively operates at either of said first and second sets of voltage levels, said voltage level shifting circuit including a transistor wherein said first terminal is a source terminal of said transistor and said second terminal is a gate terminal of said transistor, wherein said first and second terminals are selectively coupled one to said plurality of power supplies to receive either of said first and second sets of voltage amplitudes.
24. A system for protecting a circuit from excessive voltage across first and second terminals of said circuit, comprising:
means for sensing first and second voltage amplitudes at said first and second terminals, respectively;
means for generating an interim voltage amplitude;
means for coupling said interim voltage amplitude to said second terminal when said first voltage amplitude exceeds a first threshold and said second voltage amplitude is below a second threshold, wherein said interim voltage amplitude is less than said second threshold;
means for de-coupling said interim voltage amplitude from said second terminal when said second voltage amplitude exceeds said second threshold; and
means for de-coupling said interim voltage amplitude from said second terminal when said first voltage amplitude is below said first threshold.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A wireless network device comprising:
matrix modules configured to (i) receive modulated data streams, and (ii) generate matrices, wherein each of the matrix modules is configured to (i) generate one of the matrices based on channel conditions between the wireless network device and a corresponding one of a plurality of client stations, and (ii) apply the one of the matrices to each of the modulated data streams to generate multiplexed data streams;
summing modules, wherein each of the summing modules is configured to sum at least two of the multiplexed data streams to generate a transmit data stream;
a first transmitter configured to transmit a first one of the transmit data streams during a downlink transmission period to a first one of the plurality of client stations; and
a second transmitter configured to transmit a second one of the transmit data streams to a second one of the client stations while the first transmitter transmits the first one of the transmit data streams.
2. The wireless network device of claim 1, further comprising modulation modules, wherein each of the modulation modules is configured to (i) receive a data stream, and (ii) modulate the received data stream to generate one of the modulated data streams.
3. The wireless network device of claim 1, wherein the first transmitter is configured to transmit the first one of the transmit data streams during the downlink transmission period to (i) the first one of the plurality of client stations, and (ii) the second one of the plurality of client stations.
4. The wireless network device of claim 1, further comprising:
encoder modules configured to receive bit streams to generate encoded bit streams;
spatial mapping modules configured to spatially map the encoded bit streams to generate data streams; and
modulation modules configured to modulate the data streams generated by the spatial mapping modules to generate the modulated data streams.
5. The wireless network device of claim 1, further comprising modulation modules configured to (i) receive data streams from spatial mapping modules, and (ii) generate sets of orthogonal frequency division multiplexing tones, wherein:
the modulated data streams comprise the sets of orthogonal frequency division multiplexing tones; and
the matrix modules are configured to apply the matrices to the sets of orthogonal frequency division multiplexing tones to generate the multiplexed data streams.
6. The wireless network device of claim 5, wherein the modulation modules comprise quadrature amplitude modulation modules.
7. The wireless network device of claim 1, further comprising transform modules configured to outputs of the matrix modules to generate the multiplexed data streams.
8. The wireless network device of claim 7, further comprising:
cyclic prefix modules each configured to add a cyclic prefix to a respective output of one of the transform modules; and
digital-to-analog converters configured to convert outputs of the cyclic prefix modules to analog signals, wherein the analog signals include the multiplexed data streams.
9. The wireless network device of claim 1, wherein the matrix modules are configured to generate one of the matrices for one of the plurality of client stations by minimizing signal energy of signals sent to others of the plurality of client stations.
10. The wireless network device of claim 1, wherein the matrix modules are configured to generate one of the matrices for one of the plurality of client stations by maximizing a minimum signal-to-interference and noise ratio for the plurality of client stations.
11. The wireless network device of claim 1, wherein the matrix modules are configured to determine the matrices based on a signal-to-interference and noise ratio of the plurality of client stations.
12. The wireless network device of claim 1, wherein the matrix modules are configured to, for tones of the transmit data streams, adjust at least one of amplitude or phase.
13. The wireless network device of claim 1, wherein one of the first transmitter and the second transmitter is configured to transmit a signal vector s, where:
S
=
\u2211
i
=
1
N
\u2062
W
i
\u2062
x
i
;
xi is an information vector for an ith one of the plurality of client stations; and
Wi is the matrix for the ith one of the plurality of client stations.
14. The wireless network device of claim 1, further comprising a receiver configured to receive channel state information from the plurality of client stations,
wherein the matrix modules are configured to generate the matrices based on the channel state information.
15. The wireless network device of claim 1, further comprising:
a receiver; and
a channel condition estimator configured to estimate channel state information based on signals received from the plurality of client stations,
wherein the matrix modules are configured to generate the matrices based on the channel state information.
16. A method comprising:
receiving modulated data streams at matrix modules;
generating matrices via the matrix modules including (i) generating one of the matrices based on channel conditions between a wireless network device and a corresponding one of a plurality of client stations, and (ii) applying the one of the matrices to each of the modulated data streams to generate multiplexed data streams;
summing at least two of the multiplexed data streams to generate transmit data streams;
transmitting a first one of the transmit data streams during a downlink transmission period to a first one of the plurality of client stations; and
transmitting a second one of the transmit data streams to a second one of the client stations while transmitting the first one of the transmit data streams.
17. The method of claim 16, further comprising:
encoding bit streams to generate encoded bit streams;
spatially mapping, via spatial mapping modules, the encoded bit streams to generate data streams; and
modulating the data streams generated by the spatial mapping modules to generate the modulated data streams.
18. The method of claim 16, further comprising:
receiving data streams from spatial mapping modules;
generating sets of orthogonal frequency division multiplexing tones,
wherein the modulated data streams comprise the sets of orthogonal frequency division multiplexing tones; and
applying the matrices to the sets of orthogonal frequency division multiplexing tones to generate the multiplexed data streams.
19. The method of claim 16, further comprising:
transforming, via transform modules, outputs of the matrix modules to generate the multiplexed data streams;
adding a cyclic prefix to each of the outputs of the transform modules via a respective cyclic prefix module; and
converting outputs of the cyclic prefix modules to analog signals, wherein the analog signals include the multiplexed data streams.
20. The method of claim 16, further comprising:
estimating channel state information based on signals received from the plurality of client stations; and
generating the matrices based on the channel state information.