1-33. (canceled)
34. A method for controlling an oscillator, the method comprising:
generating a first control signal dependent on an output signal of the oscillator and on a first reference signal;
generating a second control signal dependent on the first control signal and on a second reference signal;
subjecting the oscillator to the first control signal and to the second control signal; and
generating the oscillator output signal with a frequency dependent on the first control signal and on the second control signal.
35. The method according to claim 34, wherein the first control signal and the second control signal are analog signals.
36. The method according to claim 34, wherein the first control signal is generated depending on a phase difference between a signal dependent on the output signal and the first reference signal.
37. The method according to claim 36, wherein the signal dependent on the output signal is generated from the output signal by a frequency division.
38. The method according to claim 34, wherein the frequency of the output signal can be varied by means of the first control signal over a first range and by means of the second control signal over a second range, wherein the second range is larger than the first range.
39. The method according to claim 38, wherein the second range is at least five times larger than the first range.
40. The method according to claim 34, wherein the frequency of the output signal of the oscillator is generated, depending on the first control signal and on the second control signal, in such a way that the derivative of the frequency of the output signal according to a signal magnitude of the first control signal is less than the derivative of the frequency of the output signal according to a signal magnitude of the second control signal, wherein the signal magnitude of the first control signal is the same as the signal magnitude of the second control signal.
41. The method according to claim 34, wherein at least one of the first control signal and the second control signal is a current signal.
42. The method according to claim 34, wherein at least one of the first control signal and the second control signal is a voltage signal.
43. The method according to claim 34, wherein at least one of the first control signal and the second control signal is a differential signal.
44. The method according to claim 34, wherein a first time constant that describes a rate of change of the first control signal under a change of the output signal of the oscillator is less than a second time constant that describes a rate of change of the second control signal under a change of the output signal of the oscillator.
45. The method according to claim 44, wherein the first time constant is less than the second time constant by at least a factor of 100.
46. The method according to claim 34, wherein the second reference signal is chosen so that it corresponds to the first control signal substantially in the middle of a signal range associated with the first control signal.
47. The method according to claim 34, wherein the second control signal is generated depending on a difference between the first control signal and the second reference signal.
48. The method according to claim 34, wherein the first reference signal is generated by a quartz oscillator.
49. An apparatus for controlling an oscillator operable to generate an output signal, the apparatus comprising:
means for generating a first control signal at a first control output, the first control signal dependent on the output signal of the oscillator and on a first reference signal;
means for generating a second control signal at a second control output, the second control signal dependent on the first control signal and on a second reference signal;
a first control input to the oscillator, the first control input connected to the first control output; and
a second control input to the oscillator, the second control input connected to the second control output; and
wherein the frequency of the output signal of the oscillator is dependent on the first control signal and on the second control signal.
50. The apparatus of claim 49, wherein the means for generating the first control signal comprise a phase detector including a first input, a second input, and an output, wherein the first input of the phase detector is connected to an output of the oscillator, and wherein the first reference signal is fed to the second input of the phase detector.
51. The apparatus of claim 50, wherein the means for generating the first control signal further comprise a loop filter including an input and an output, wherein the input of the loop filter is connected to the output of the phase detector, and wherein the output of the loop filter is connected to the first control input of the oscillator and to an input of the means for generating the second control signal.
52. The apparatus of claim 49, further comprising a frequency divider including an input and an output, wherein the input of the frequency divider is connected to an output of the oscillator and the output of the frequency divider is connected to an input of the means for generating the first control signal.
53. The apparatus of claim 49, wherein the means for generating the second control signal comprise an amplifier including a first input, a second input and an output, wherein the first input of the amplifier is connected to the first control output, wherein the output of the amplifier is connected to the second control output, wherein the second reference signal is fed to the second input of the amplifier, and wherein the amplifier is designed so that it amplifies a difference between the first control signal and the second reference signal and issues at the output of the amplifier a signal corresponding to the amplified difference.
54. The apparatus of claim 53, wherein the amplifier is a transconductance amplifier.
55. The apparatus according to claim 53, wherein the means for generating the second control signal comprise a capacitance that is designed and is connected to the output of the amplifier in such a way that it integrates the signal present at the output of the amplifier in order to generate the second control signal.
56. The apparatus of claim 49, wherein the means for generating the second control signal comprise switching means that are designed so that the means for generating the second control signal can be switched with the switching means between a first operating mode and a second operating mode, wherein in the first operating mode the second control signal can be changed, and wherein in the second operating mode the second control signal cannot be changed.
57. The apparatus of claim 56, further comprising control means for controlling the switching means, the control means operable to switch the switching means in a specific timing ratio between the first operating mode and the second operating mode.
58. The apparatus of claim 57, wherein the timing ratio between a duration of the first operating mode and a duration of the second operating mode is of the order of magnitude of 1:1000.
59. The apparatus of claim 55, wherein the means for generating the second control signal comprise switching means that are designed so that the means for generating the second control signal can be switched with the switching means between a first operating mode and a second operating mode, wherein in the first operating mode the second control signal can be changed, wherein in the second operating mode the second control signal cannot be changed, and further comprising a dummy circuit connected to the output of the amplifier and to a terminal of the capacitance, wherein the dummy circuit is designed so that the output of the amplifier and the terminal of the capacitance can be maintained at the same potential when the switching means are in the second operating mode.
60. The apparatus of claim 49, wherein the oscillator comprises an LC element for generating the output signal, wherein the LC element comprises a first adjustable capacitance and a second adjustable capacitance, wherein an adjustment input of the first capacitance is connected to the first control input and an adjustment input of the second capacitance is connected to the second control input.
61. The apparatus of claim 60, wherein the second adjustable capacitance has a larger adjustment range than the first adjustable capacitance.
62. The apparatus of claim 60, wherein at least one of the first adjustable capacitance and the second adjustable capacitance comprises a varactor.
63. The apparatus of claim 49, wherein the apparatus is designed such that the frequency of the output signal of the oscillator is generated, depending on the first control signal and on the second control signal, in such a way that the derivative of the frequency of the output signal according to a signal magnitude of the first control signal is less than the derivative of the frequency of the output signal according to a signal magnitude of the second control signal, wherein the signal magnitude of the first control signal is the same as the signal magnitude of the second control signal.
64. The apparatus of claim 49, wherein the apparatus is designed such that a first time constant, which describes a rate of change of the first control signal under a change of the output signal of the oscillator, is less than a second time constant that describes a rate of change of the second control signal under a change of the output signal of the oscillator.
65. The apparatus of claim 64, wherein the first time constant is less than the second time constant by at least a factor of 100.
66. A phase locked loop comprising:
an oscillator comprising a first control input, a second control input, and an output, the oscillator operable to generate an output signal at the oscillator output;
a first control device including a first control output connected to the first control input of the oscillator, the first control device operable to generate a first control signal at the first control output, wherein the first control signal is dependent on the output signal of the oscillator and on a first reference signal; and
a second control device including a second control output connected to the second control input of the oscillator, the second control device also connected to the first control output, the second control device operable to generate a second control signal at the second control output, wherein the second control signal is dependent on the first control signal and on a second reference signal;
wherein the oscillator is designed so that it generates the output signal with a frequency dependent on the first control signal and on the second control signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An equalization method, comprising:
obtaining, by an equalizer, a reference sample of an input signal, the reference sample having a reference sample value;
obtaining, by the equalizer, a set of shifted input signal samples at a sample period of one unit interval, the samples being shifted by a delay value, the delay value being less than the sample period, the obtained samples being strongly correlated with future and past transmitted bits and being weakly correlated with future and past bit transitions;
multiplying, by the equalizer, each element of said set of samples by a filter coefficient weight to create a set of compensation values; and
generating, by the equalizer, an output as a sum of the compensation values and the reference sample value.
2. The method of claim 1 wherein the set of shifted input samples are shifted with respect to an eye-center-aligned timing reference.
3. The method of claim 1 wherein the set of shifted input samples are shifted with respect to an eye-edge-aligned timing reference.
4. The method of claim 1 wherein obtaining the set of shifted input samples that are strongly correlated with future and past transmitted bits comprises only obtaining the samples at time instants that are more than the sample period away from the reference sample.
5. The method of claim 1 wherein:
the first reference sample of the input signal is taken at instant t, and
the set of shifted input samples are taken at instants t+p+nT,
where p represents the delay value, which is a fixed timing shift in the range 0, T,
where T is the period of a data symbol, and
where n is an integer and spans a range of values set by the desired filter length, but excludes values \u22121 and 0.
6. The method of claim 1 wherein the delay value is a fixed value.
7. The method of claim 1 wherein the delay value is T2.
8. The method of claim 1 wherein the delay value is variable and is set to optimize a performance criterion.
9. The method of claim 1 wherein the delay value is variable and is set to minimize the sum of squares of FFE coefficients.
10. The method of claim 1 wherein the delay value is variable and is set to minimize the sum of squares of the difference between the output signal and a ideally equalized input signal.
11. The method of claim 1 further comprising:
obtaining, by the equalizer, a second set of samples at the sample period of one unit interval, the samples being shifted by the delay value;
multiplying, by the equalizer, the second set of samples with a second set of filter coefficients to create a second set of compensation values;
adding, by the equalizer, the sum of the second set of compensation values to the output; and
adjusting, by the equalizer, the second set of filter coefficients to produce a desired timing point delay.
12. An equalization circuit comprising:
a first signal sampler configured to obtain a reference sample of an input signal, the reference sample having a reference sample value;
a second signal sampler configured to obtain a set of shifted input signal samples at a sample period of one unit interval, the samples being shifted by a delay value, the delay value being less than the sample period, the obtained samples being strongly correlated with future and past transmitted bits and being weakly correlated with future and past bit transitions; and
a multiplier circuit configured to multiply each element of said set of samples by a filter coefficient weight to create a set of compensation values, and to generate an output as a sum of the compensation values and the reference sample value.
13. The equalization circuit of claim 12 wherein the second signal sampler is configured to only obtain the samples at time instants that are more than the sample period away from the reference sample.
14. The equalization circuit of claim 12 wherein:
the first signal sampler is configured to produce signal samples at instants t0+nT,
where t0 is an initial time reference, n is an integer and T is a symbol period corresponding to the sample period; and
the second signal sampler is configured to produce signal samples at instants t0+nT+p,
where p is a constant in the range 0, T.
15. The equalization circuit of claim 12 further comprising:
a non-transitory machine-readable readable medium storing a set of filter coefficients including a main filter coefficient; and
a summing element having one input for each filter coefficient element and producing the output signal;
wherein the multiplier circuit comprises:
a) a first multiplying element having:
i) a first input connected to the main filter coefficient;
ii) a second input connected to the sample from the first signal sampler;
iii) an output connected to one of the inputs of the summing element;
b) a set of multiplying elements, each having:
i) a first input connected to one of the filter coefficients;
ii) a second input connected to one of the stored samples from the second signal sampler, the stored samples being selected according to the filter length, but omitting samples t0+nT+p and t0+(n\u22121)T+p, when processing the sample from the first sampler taken at instant t0+nT; and
iii) an output connected to one of the inputs of the summing element.
16. The equalization circuit of claim 15 wherein:
the first and second signal samplers are implemented as analog-to-digital converters; and
the summing element, the non-transitory machine readable medium, the first multiplying element and the set of multiplying elements are implemented using digital circuits.
17. The equalization circuit of claim 12 wherein the summing element comprises two supplemental inputs, and further comprising:
two supplemental coefficients set to obtain a desired timing instant variation; and
two further multiplying elements, each having:
i) a first input connected to the stored samples from the second sampler corresponding to samples at instant t0+nT+p and t0+(n\u22121)T+p, when processing the sample from the first sampler taken at instant t0+nT
ii) a second input connected to one of each of said supplemental coefficients; and
iii) an output connected to one of each of said supplemental summing node inputs.
18. An equalization circuit comprising:
a first signal sampler configured to obtain a reference sample of an input signal, the reference sample having a reference sample value, and to produce signal samples at instants t0+nT, where t0 is an initial time reference, n is an integer and T is a symbol period corresponding to the sample period; and
a second signal sampler configured to obtain a set of shifted input signal samples at a sample period of one unit interval, the samples being shifted by a delay value, the delay value being less than the sample period, the obtained samples being strongly correlated with future and past transmitted bits and being weakly correlated with future and past bit transitions, the second signal sampler being configured to produce signal samples at instants t0+nT+q, where q is a constant in the range \u2212T2,T2; and
a multiplier circuit configured to multiply each element of said set of samples by a filter coefficient weight to create a set of compensation values, and to generate an output as a sum of the compensation values and the reference sample value.
19. An equalization circuit comprising:
a. a first signal sampler producing a signal sample at instants t0+nT, where t0 is an initial time reference synchronized close to the edge of each unit interval (UI), n is an integer and T is a symbol period;
b. a second signal sampler producing a signal sample at instants t0+nT+T2;
c. a set of filter coefficients
d. means to store the samples from the first and second signal samplers
e. a first summing element having one input for each filter coefficient element and producing a timing recovery output signal
f. a first multiplying element having
i. a first input connected to the main filter coefficient for timing recovery
ii. a second input connected to a main sample from the first signal sampler
iii. an output connected to one of the inputs of said first summing element for timing recovery
g. a first set of multiplying elements, each having:
i. a first input connected to one of said filter coefficients
ii. a second input connected to one of the stored samples from the second signal samplers, stored samples are selected according to the filter length, but ignore samples t0+nT+T2 and t0+(n\u22121)T+T2, when processing the sample from the first sampler taken at instant t0+nT
iii. an output connected to one of the inputs of said summing element
h. a second summing element having one input for each filter coefficient element and producing a data recovery output signal
i. a second multiplying element having
i. a first input connected to the main filter coefficient for data recovery
ii. a second input connected to a main sample from the second signal sampler
iii. an output connected to one of the inputs of said second summing element for data recovery
j. a second set of multiplying elements, each having:
i. a first input connected to one of said filter coefficients
ii. a second input connected to one of the stored samples from the first signal samplers, stored samples are selected according to the filter length, but ignore samples t0+(n+1) T and t0+nT, when processing the sample from the first sampler taken at instant t0+nT+T2
iii. an output connected to one of the inputs of said second summing element for data recovery.
20. The circuit of claim 19 wherein:
the first and second signal samplers are implemented as analog-to-digital converters; and
the summing element, the non-transitory machine readable medium, the first and second multiplying elements and the first and second sets of multiplying elements are implemented using digital circuits.
21. The circuit of claim 19 wherein the summing element comprises two supplemental inputs, and further comprising:
two supplemental coefficients set to obtain a desired timing instant variation; and
two further multiplying elements, each having:
i. a first input connected to the stored samples from the second sampler corresponding to samples at instant t0+nT+T2 and t0+(n\u22121)T+T2, when processing the sample from the first sampler taken at instant t0+nT
ii. a second input connected to one of each of said supplemental coefficients; and
iii. an output connected to one of each of said supplemental first summing node inputs.