1. A method of manufacturing a semiconductor device, comprising:
preparing an initial substrate including an edge region and a central region, the central region including circuit patterns;
forming a reforming region in the edge region of the initial substrate;
grinding the initial substrate to form a substrate; and
cutting the substrate to form a semiconductor chip including each of the circuit patterns,
wherein a crystal structure of the reforming region is different from a crystal structure of the initial substrate.
2. The method as set forth in claim 1, wherein forming the reforming region in the edge region of the initial substrate comprises irradiating a laser along the edge region of the initial substrate.
3. The method as set forth in claim 1, wherein a depth of the reforming region is between about 70 percent and about 99 percent of a thickness of the initial substrate.
4. The method as set forth in claim 1, wherein the reforming region is exposed to a ground surface of the substrate.
5. The method as set forth in claim 1, wherein forming the reforming region in the edge region of the initial substrate includes substantially continuously irradiating a laser along the edge region of the initial substrate.
6. The method as set forth in claim 1, wherein forming the reforming region in the edge region of the initial substrate includes intermittently irradiating a laser along the edge region of the initial substrate to form a plurality of patterns.
7. The method as set forth in claim 1, wherein forming the reforming region in the edge region of the initial substrate comprises:
irradiating a laser along the edge region of the initial substrate to form a first pattern; and
irradiating the laser between the first pattern and the edge of the initial substrate to form a second pattern.
8. The method as set forth in claim 1, wherein
the initial substrate includes a notch, and
forming the reforming region in the edge region of the initial substrate includes irradiating a laser to a portion adjacent to the notch of the initial substrate.
9. The method as set forth in claim 8, wherein forming the reforming region in the edge region of the initial substrate further comprises irradiating the laser along the edge region of the initial substrate.
10. A method of manufacturing a semiconductor, comprising:
forming a substrate having a first thickness and including an edge region and a central region, the central region including a plurality of patterns;
attaching a carrier substrate to the substrate; and
irradiating the edge region with a laser to form a reforming region having a crystalline structure that is different from a crystalline structure of the central region.
11. The method of claim 10, further comprising:
grinding the substrate to a second thickness smaller than the first thickness;
separating the carrier substrate from the substrate; and
cutting the substrate to form a plurality of semiconductor chips.
12. The method of claim 11, wherein the plurality of semiconductor chips correspond to the plurality of patterns.
13. The method of claim 10, wherein a depth of the reforming region is between about 70 percent and about 99 percent of the first thickness.
14. The method of claim 10, wherein irradiating the edge region comprises substantially continuously irradiating the laser along the edge region.
15. The method of claim 10, wherein irradiating the edge region comprises intermittently irradiating the laser along the edge region.
16. The method of claim 10, wherein irradiating the edge region comprises forming a first pattern and a second pattern.
17. The method of claim 16, wherein the first pattern and the second pattern are concentric.
18. The method of claim 10, wherein the substrate comprises a notch displaying a crystal orientation of the substrate.
19. The method of claim 18, wherein irradiating the edge region comprises forming a first pattern and a second pattern, the second pattern being between the first pattern and the edge region;
the first pattern being conformal to a circumference of the substrate and to the notch; and
the second pattern being formed at the notch.
20. The method of claim 19, wherein the first pattern is one of
a closed curve formed along the circumference of the substrate; and
including a plurality of separate patterns formed along the circumference of the substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit comprising:
first processing circuitry configured to perform processing upon an input signal to generate an output signal;
second processing circuitry coupled to said first processing circuitry and configured to perform further processing upon said output signal;
error detecting circuitry configured to detect errors in said output signal at a time after said second processing circuitry has started to perform said further processing using said output signal;
error repair circuitry configured to respond to an error in said output signal detected by said error detecting circuitry to perform an error repair operation;
error tolerance circuitry coupled to said error repair circuitry and configured to respond to a control parameter to selectively disable said error repair circuitry such that said error repair operation is not performed; and
storage circuitry configured to store a plurality of output signals values and error status for said plurality of data values; wherein
said control parameter is dependent upon at least some of said plurality of output signal values and error status for said plurality of signal values stored within said storage circuitry.
2. An integrated circuit as claimed in claim 1, wherein said control parameter is dependent upon said output signal generated by said processing of said first processing circuitry, such that if said error in said output signal results in said output signal being inside a fault-tolerated range, then said error repair circuitry is disabled.
3. An integrated circuit as claimed in claim 2, wherein said output signal is a multi-bit signal and said fault-tolerated range comprises a range of normal values within a maximum possible range of values.
4. An integrated circuit as claimed in claim 2, wherein said output signal is a multi-bit signal and said fault-tolerated range comprises values with less than a threshold difference from at least one temporally neighbouring value stored within said storage circuitry.
5. An integrated circuit as claimed in claim 1, wherein said control parameter is dependent upon said output signal generated by said processing of said first processing apparatus, such that if said error in said output signal results in fewer than a threshold number successive output signals generated by said first processing circuitry and stored within said storage circuitry being in error, then said error repair circuitry is disabled.
6. An integrated circuit comprising:
first processing means for performing processing upon an input signal to generate an output signal;
second processing means for performing further processing upon said output signal, said second processing means coupled to said first processing means;
error detecting means for detecting errors in said output signal at a time after said second processing means has started to perform said further processing using said output signal;
error repair means for responding to an error in said output signal detected by said error detecting means to perform an error repair operation;
error tolerance means for selectively disable said error repair means such that said error repair operation is not performed in respond to a control parameter; and
storage means for storing a plurality of output signals values and error status for said plurality of data values; wherein
said control parameter is dependent upon at least some of said plurality of output signal values and error status for said plurality of signal values stored within said storage means.
7. A method of operating an integrated circuit comprising the steps of:
performing processing using first processing circuitry upon an input signal to generate an output signal;
performing further processing upon said output signal using second processing circuitry coupled to said first processing circuitry;
detecting errors in said output signal at a time after said second processing circuitry has started to perform said further processing using said output signal;
in response to an error in said output signal detected by said detecting step, performing an error repair operation;
in response to a control parameter, selectively disabling said error repair step such that said error repair operation is not performed; and
storing a plurality of output signals values and error status for said plurality of data values; wherein
said control parameter is dependent upon at least some of said plurality of output signal values and error status for said plurality of signal values stored in said storing step.
8. A method as claimed in claim 7, wherein said control parameter is dependent upon said output signal generated by said processing of said first processing circuitry, such that if said error in said output signal results in said output signal being inside a fault-tolerated range, then said error repair circuitry is disabled.
9. A method as claimed in claim 8, wherein said output signal is a multi-bit signal and said fault-tolerated range comprises a range of normal values within a maximum possible range of values.
10. A method as claimed in claim 8, wherein said output signal is a multi-bit signal and said fault-tolerated range comprises values with less than a threshold difference from at least one temporally neighbouring value stored within said storage circuitry.
11. A method as claimed in claim 7, wherein said control parameter is dependent upon said output signal generated by said processing of said first processing circuitry, such that if said error in said output signal results in fewer than a threshold number successive output signals generated by said first processing circuitry and stored within said storage circuitry being in error, then said error repair circuitry is disabled.