1. An embedded-DRAM (dynamic random access memory) processing system comprising:
an embedded processor comprising one or more functional units;
a DRAM array comprising a plurality of memory cells arranged in rows and columns;
a row address register configured to store a pointer that references a row of the DRAM array; and
one or more dual-port register files, wherein each dual-port register file comprises a plurality of data registers, and wherein each dual-port register file comprises:
a first port configured to parallely transfer data between a selected dual-port register file and the referenced row; and
a second port configured to transfer data between the selected dual-port register file and one of the functional units.
2. The embedded-DRAM processing system of claim 1, wherein each dual-port register file comprises at least one dual-port static random access memory (SRAM) cell.
3. The embedded-DRAM processing system of claim 1, wherein each of the dual-port register files is capable of loading data from or storing data to the entire referenced row of the DRAM array in a single operation.
4. The embedded-DRAM processing system of claim 3, comprising an instruction set comprising:
a first command for performing an arithmetic operation on the row address register;
a second command for activating the row referenced by the pointer;
a third command for deactivating the row referenced by the pointer subsequent to the referenced row being activated by the second command; and
a fourth command for loading data from selected columns of the entire activated row into a set of data registers of one of the one or more dual-port register files in a single operation.
5. A method for loading data, comprising:
using a pointer stored in a row address register to identify a row of a DRAM array;
issuing a first command to activate the row referenced by the pointer;
selecting a set of columns within the activated row using a bit mask;
issuing a second command to cause data stored in the selected set of columns of the activated row to be loaded into a set of data registers within a register file in a single operation; and
issuing a third command to deactivate the activated row.
6. The method of claim 5, wherein activating the referenced row comprises precharging the referenced row.
7. The method of claim 5, comprising issuing a fourth command for performing an arithmetic operation on the row address register.
8. The method of claim 5, comprising issuing a fifth command for manipulating bits in the bit mask.
9. The method of claim 5, comprising issuing a sixth command to toggle the register file between an active state and an inactive state based at least partially upon whether data stored in the register file is being assembled by a data assembly unit.
10. The method of claim 5, wherein the second command causes the entire activated row to be loaded into the set of data register when every column of the activated row is selected by the bit mask.
11. A data processing device, comprising:
a DRAM array comprising a plurality of memory cells arranged in rows and columns;
first and second register files each comprising a plurality of data registers, wherein each of the first and second register files is capable of storing an entire row of the DRAM array in response in response to a single command, and wherein each of the first and second register files is capable of entering an active state and an inactive state;
a set of functional units configured to perform logical operations on data accessed from the first register file when the first register file is in the active state and from the second register file when the second register file is in the active state; and
an instruction set comprising:
a first command to load data from selected columns of an entire selected row of the DRAM array into a set of data registers of one of either the first or second register files in a single operation; and
a second command for toggling each of the first and second register files between the active state and the inactive state.
12. The data processing device of claim 11, wherein the execution of the second command causes the first register file to toggle from the inactive state to the active state, and causes the second register file to toggle from the active state to the inactive state.
13. The data processing device of claim 11, comprising a data assembly unit configured to assemble data stored in the first and second register files:
wherein the first register file is determined to be in the inactive state if data stored within the first register file is being assembled by the data assembly unit, and to be in the active state when the data assembly unit completes assembling the data stored within the first register file; and
wherein the second register file is determined to be in the inactive state if data stored within the second register file is being assembled by the data assembly unit, and to be in the active state when the data assembly unit completes assembling the data stored within the second register file.
14. The data processing device of claim 13, wherein the data assembly unit comprises an instruction register configured to receive a first set of instructions from a main instruction stream of a processor, and a second set of instructions from an execution thread stored in program memory.
15. The data processing device of claim 13, wherein the data assembly unit comprises:
a mask register; and
a mask logic unit configured to manipulate data in the mask register, wherein the information stored in the mask register is output from the data assembly unit via a control line.
16. The data processing device of claim 15, comprising a mask and switch unit configured to receive the mask register information via the control line and to select a set of data registers from either the first register file or the second register by manipulating bits of a bit mask using the received mask register information.
17. The data processing device of claim 16, wherein the first command causes the entire selected row of the DRAM array to be loaded into the set of data registers in a single operation when all columns of the selected row are selected by the bit mask.
18. The data processing device of claim 17, wherein the instruction set comprises a third command for manipulating the bits in the bit mask.
19. The data processing device of claim 11, wherein the set of functional units comprises:
a dispatch unit configured to dispatch one or more instruction streams; and
a plurality of functional units each being configured to execute a respective one of the one or more instruction streams dispatched by the dispatch unit.
20. An embedded-DRAM (dynamic random access memory) processing device comprising:
a DRAM array comprising a plurality of memory cells arranged in rows and columns;
a row address register configured to store a pointer that references a row of the DRAM array;
one or more register files, wherein each register file comprises a plurality of data registers, and wherein each register file is capable of storing an entire row of the DRAM array in response in response to a single command; and
an instruction set comprising:
a first command for performing an arithmetic operation on the row address register;
a second command for activating the row referenced by the pointer;
a third command for deactivating the row referenced by the pointer subsequent to the referenced row being activated by the second command; and
a fourth command for loading data from selected columns of the entire activated row into a set of data registers of a register file in a single operation.
21. The embedded-DRAM processing device of claim 20, wherein activating the referenced row comprises precharging the referenced row.
22. The embedded-DRAM processing device of claim 20, wherein the selected columns are selected based upon the state of a plurality of bits within a bit mask.
23. The embedded-DRAM processing device of claim 22, wherein the fourth command causes the entire activated row to be loaded into the set of data registers when all columns of the activated row are selected by the bit mask.
24. The embedded-DRAM processing device of claim 20, wherein the one or more register files comprises a first register file being in an active state and a second register file being in an inactive state.
25. The embedded-DRAM processing device of claim 24, comprising:
a first functional unit configured to execute a fifth command for processing the contents of a data register within the active register file; and
a second functional unit configured to execute a sixth command for parallely transferring data between the inactive register file and the DRAM array.
26. The embedded-DRAM processing device of claim 25, wherein the fifth and sixth commands are executed substantially contemporaneously.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A receptor holder comprising:
a connection end operable to couple the receptor holder to a collimator tube;
a bar coupled to the connection end;
a holder end coupled to the bar, said holder end having a sensor docking port;
a wire coupled to the connection end and the sensor docking port; and
wherein the receptor holder is operable to allow digital data to be transmitted from a sensor docked on the docking port through the wire and to the connection end.
2. The receptor holder of claim 1, wherein the wire is contained within the bar.
3. The receptor holder of claim 1, wherein the bar contains a radio frequency transmitter, said radio frequency transmitter being operable to transmit digital images to a computer device.
4. The receptor holder of claim 1, wherein the holder end is operable to hold an x-ray film.
5. The receptor holder of claim 1, wherein the connection end is square in cross section shape.
6. The receptor holder of claim 1, wherein the connection end is rectangular in cross section shape.
7. The receptor holder of claim 1, wherein the bar is adjustable.
8. The receptor holder of claim 7, wherein the bar includes notches which are operable to indicate the distance between the connection end and the holder end.
9. The receptor holder of claim 1, wherein the holder end is operable to hold a mirror.
10. A receptor holder adapted for use with a collimator tube and an X-ray generator; the collimator tube having a contact sensor receptacle; the receptor holder comprising:
a connection end operable to couple the receptor holder to the collimator tube;
a contact sensor on said connection end adapted to connect with the contact sensor receptacle when said connection end is coupled to the collimator tube;
a bar coupled to said connection end;
a holder end coupled to the bar;
wherein said contact sensor completes an electrical circuit with the contact sensor receptacle.
11. The receptor holder of claim 10, wherein a light illuminates when said contact sensor connects with the contact sensor receptacle.
12. The receptor holder of claim 10, wherein an audible sound is emitted when said contact sensor connects with the contact sensor receptacle.
13. The receptor holder of claim 10, wherein the X-ray generator will not fire unless said contact sensor is connected with the contact sensor receptacle.
14. The receptor holder of claim 10, further comprising:
a sensor docking port located in the holder end, said sensor docking port operable to make an electrical connection with an X-ray sensor docked on the docking port.
15. The receptor holder of claim 14, further comprising:
a radio frequency transmitter electrically mated to the sensor docking port when said connection end is coupled to the collimator tube;
wherein said radio frequency transmitter is operable to transmit digital data from a sensor docked on the docking port.
16. The receptor holder of claim 10, wherein the receptor holder is operable to be magnetically coupled to the collimator tube when the receptor holder is positioned adjacent to the collimator tube.
17. The receptor holder of claim 16, further comprising:
a metal snap ring coupled to the connecting end;
wherein said snap ring contacts a magnet in the collimator tube when the receptor holder is positioned adjacent to the collimator tube;
wherein said snap ring is said contact sensor.
18. A receptor holder adapted to hold an X-ray sensor, the receptor holder also adapted to be used with a collimator tube, the receptor holder comprising:
a connection end operable to couple the receptor holder to the collimator tube;
a bar coupled to said connection end;
a holder end coupled to the bar;
a sensor docking port on said holder end, said sensor docking port operable to make an electrical connection with the X-ray sensor when docked on the docking port.
19. The receptor holder of claim 18, further comprising a contact end coupled to said bar proximate to said connection end, said contact end being operable to make an electrical connection with the collimator tube.
20. The receptor holder of claim 19, further comprising a wire which electrically couples said contact end to said sensor docking port.
21. The receptor holder of claim 18, wherein the holder end is operable to hold a digital charge-coupled sensor.
22. The receptor holder of claim 18, further comprising a contact sensor on the connection end operable to connect with a contact sensor receptacle in the collimator tube when said connection end is coupled to the collimator tube.
23. The receptor holder of claim 18, wherein the holder end is operable to hold an X-ray film.
24. The receptor holder of claim 18, wherein said electrical connection is an edge contact connection.