1. A system comprising:
an integrated circuit comprising a digital logic circuit, a memory refresh circuit, and one or more dynamic random access memory (DRAM) cells, wherein:
said one or more DRAM cells is refreshed by said memory refresh circuit;
said one or more DRAM cells store data received via a communication link; and
a rate at which said one or more DRAM cells is refreshed is adjusted based on a symbol rate at which said data is received via said communication link.
2. The system of claim 1, wherein each of said one or more DRAM cells and said second one or more DRAM cells is a one-transistor (\u201c1T\u201d) cell.
3-7. (canceled)
8. The system of claim 1, wherein said adjustment of said rate at which said one or more DRAM cells is refreshed comprises an enabling of refresh of said one or more DRAM cells by said memory refresh circuit during a first time interval and a disabling of refresh of said one or more DRAM cells by said memory refresh circuit during a second time interval.
9. The system of claim 1, wherein said adjustment of said rate at which said one or more DRAM cells is refreshed is based on a forward error correction code rate of said data.
10-20. (canceled)
21. The system of claim 1, wherein:
said adjustment of said rate at which said one or more DRAM cells is refreshed comprises a disabling of refresh of said one or more DRAM cells when said symbol rate is above a determined threshold; and
said adjustment of said rate at which said one or more DRAM cells is refreshed comprises an enabling of refresh of said one or more DRAM cells when said symbol rate is below said determined threshold.
23. The system of claim 1, wherein said adjustment of said rate at which said one or more DRAM cells is refreshed is performed during run-time of said integrated circuit.
24. A system comprising:
an integrated circuit comprising a digital logic circuit, a memory refresh circuit, and one or more dynamic random access memory (DRAM) cells, wherein:
said one or more DRAM cells is refreshed by said memory refresh circuit; and
a rate at which said one or more DRAM cells is refreshed is adjusted based on error tolerance of data stored in said one or more DRAM cells.
25. The system of claim 24, wherein each of said one or more DRAM cells and said second one or more DRAM cells is a one-transistor (\u201c1T\u201d) cell.
26. The system of claim 24, wherein said adjustment of said rate at which said one or more DRAM cells is refreshed comprises an enabling of refresh of said one or more DRAM cells by said memory refresh circuit during a first time interval and a disabling of refresh of said one or more DRAM cells by said memory refresh circuit during a second time interval.
27. The system of claim 24, wherein said adjustment of said rate at which said one or more DRAM cells is refreshed is based on a forward error correction code rate of said data.
28. The system of claim 24, wherein:
said adjustment of said rate at which said one or more DRAM cells is refreshed comprises a disabling of refresh of said one or more DRAM cells when said error tolerance is above a determined threshold; and
said adjustment of said rate at which said one or more DRAM cells is refreshed comprises an enabling of refresh of said one or more DRAM cells when said symbol rate is below said determined threshold
29. The system of claim 24, wherein said adjustment of said rate at which said one or more DRAM cells is refreshed is performed during run-time of said integrated circuit.
30. A system comprising:
an integrated circuit comprising a digital logic circuit, a memory refresh circuit, and one or more dynamic random access memory (DRAM) cells, wherein:
said one or more DRAM cells is refreshed by said memory refresh circuit; and
a rate at which said one or more DRAM cells is refreshed is adjusted based on a forward error correction code rate of data stored in said one or more DRAM cells.
31. The system of claim 30, wherein each of said one or more DRAM cells and said second one or more DRAM cells is a one-transistor (\u201c1T\u201d) cell.
32. The system of claim 30, wherein said adjustment of said rate at which said one or more DRAM cells is refreshed comprises an enabling of refresh of said one or more DRAM cells by said memory refresh circuit during a first time interval and a disabling of refresh of said one or more DRAM cells by said memory refresh circuit during a second time interval.
33. The system of claim 30, wherein:
said adjustment of said rate at which said one or more DRAM cells is refreshed comprises a disabling of refresh of said one or more DRAM cells when said error tolerance is above a determined threshold; and
said adjustment of said rate at which said one or more DRAM cells is refreshed comprises an enabling of refresh of said one or more DRAM cells when said symbol rate is below said determined threshold
34. The system of claim 30, wherein said adjustment is performed during run-time of said integrated circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A run-flat tire comprising
a carcass extending between bead cores each disposed in a first bead portion and a second bead portion, through a tread portion and sidewall portions,
a pair of side reinforcing rubber layers made of rubber having a high hardness, and each having a crescent cross-sectional shape and disposed axially inside the carcass in each sidewall portion, and
a pair of sidewall rubber components each disposed axially outside the carcass in each sidewall portion,
wherein the side reinforcing rubber layers comprise a first side reinforcing rubber layer disposed in the side of the first bead portion, and a second side reinforcing rubber layer disposed in the side of the second bead portion,
wherein the sidewall rubber components comprise a first sidewall rubber component disposed in the side of the first bead portion, and a second sidewall rubber component disposed in the side of the second bead portion, and
wherein at a tire maximum-width position in a tire cross section including a tire axis under a standard condition in which the tire is mounted on a standard rim and is inflated to a standard pressure, but no tire load is loaded, the first side reinforcing rubber layer has a thickness B1 greater than a thickness B2 of the second side reinforcing rubber layer, and the first sidewall rubber component has a thickness A1 smaller than a thickness A2 of the second sidewall rubber component.
2. The run-flat tire according to claim 1,
wherein a loss tangent (tan \u03b41) of the sidewall rubber component is greater than a loss tangent (tan \u03b42) of the side reinforcing rubber layer in each sidewall portion, and
wherein a complex elastic modulus E*1 of the sidewall rubber component is smaller than a complex elastic modulus E*2 of the side reinforcing rubber layer in each sidewall portion.
3. The run-flat tire according to claim 1,
wherein the respective thicknesses A1, A2, B1 and B2 satisfy the following relation:
0.9\u2266(A1+B1)(A2+B2)\u22661.1.
4. The run-flat tire according to claim 1,
wherein the respective thicknesses A1, A2, B1 and B2 satisfy the following relations:
1.4\u2266A2A1\u22662.0; and
1.15\u2266B1B2\u22661.4.
5. A method for mounting the run-flat tire according to claim 1 on a four-wheeled vehicle, comprising a step of
mounting the run-flat tire on a rear wheel of the four-wheeled vehicle so that the first bead portion is arranged at an inboard of the rear wheel.
6. A method for mounting the run-flat tire according to claim 1 on a four-wheeled vehicle, comprising a step of
mounting the run-flat tire on a front wheel of the four-wheeled vehicle so that the first bead portion is arranged at an outboard of the front wheel.
7. The run-flat tire according to claim 2,
wherein the respective thicknesses A1, A2, B1 and B2 satisfy the following relation:
0. 9\u2266(A1+B1)(A2+B2)\u22661.1.
8. The run-flat tire according to claim 2,
wherein the respective thicknesses A1, A2, B1 and B2 satisfy the following relations:
1.4\u2266A2A1<2.0; and
1.15\u2266B1B2\u22661.4.
9. The run-flat tire according to claim 3,
wherein the respective thicknesses A1, A2, B1 and B2 satisfy the following relations:
1.4\u2266A2A1\u22662.0; and
1.15\u2266B1B2\u22661.4.
10. A method for mounting the run-flat tire according to claim 2 on a four-wheeled vehicle, comprising a step of
mounting the run-flat tire on a rear wheel of the four-wheeled vehicle so that the first bead portion is arranged at an inboard of the rear wheel.
11. A method for mounting the run-flat tire according to claim 3 on a four-wheeled vehicle, comprising a step of
mounting the run-flat tire on a rear wheel of the four-wheeled vehicle so that the first bead portion is arranged at an inboard of the rear wheel.
12. A method for mounting the run-flat tire according to claim 4 on a four-wheeled vehicle, comprising a step of
mounting the run-flat tire on a rear wheel of the four-wheeled vehicle so that the first bead portion is arranged at an inboard of the rear wheel.
13. A method for mounting the run-flat tire according to claim 2 on a four-wheeled vehicle, comprising a step of
mounting the run-flat tire on a front wheel of the four-wheeled vehicle so that the first bead portion is arranged at an outboard of the front wheel.
14. A method for mounting the run-flat tire according to claim 3 on a four-wheeled vehicle, comprising a step of
mounting the run-flat tire on a front wheel of the four-wheeled vehicle so that the first bead portion is arranged at an outboard of the front wheel.
15. A method for mounting the run-flat tire according to claim 4 on a four-wheeled vehicle, comprising a step of
mounting the run-flat tire on a front wheel of the four-wheeled vehicle so that the first bead portion is arranged at an outboard of the front wheel.