1. In combination a container whose purpose is the confinement of some substance, a substance-usually liquid-subject to spillage, a unitary corrugated discoid protecting device for positioning towards the top of the container close to the substance, thereby preventing spillage onto said container or objects nearby, said device comprising the combination of a spacing at its center to house the container with an entrance hole on the top (slightly larger in diameter than a chosen location on the container) and bottom (identical in diameter to that same location), inside of which exists corrugated fluting running the length of the device from its corecenter to its outer edge.
2. The combination as claimed in claim 1 wherein said device possesses an aggregate opening at its center with the top opening and bottom opening being of differing widthsdiameters, thus creating a slope between them.
3. The combination as claimed in claim 1 wherein said device contains at its heart corrugated fluting running throughout from the core to the edges.
4. The combination as claimed in claim 1 wherein said device is formed of a biodegradable and moisture-resistant, leak-proof material such as corrugated cardboard.
5. The combination as claimed in claim 1 wherein said device possesses a foldable base or shield that’s slightly larger in diameter than the adhesively joined top surface and interior corrugated fluting, which, when folded, creates an overlapping floral petal pattern.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory device, comprising:
a pre-driving unit configured to output a state output signal transitioning between a power supply voltage and a source voltage in response to code signals containing address information for cells;
a driving unit configured to output a selection signal to activate a corresponding one of the cells in response to the state output signal; and
a source voltage control unit configured to provide the source voltage whose voltage level changes depending on an operational mode of the semiconductor memory device,
wherein the pre-driving unit includes at least one PMOS transistor and at least one NMOS transistor to receive a pumping voltage and a back-bias voltage, respectively, through their bulk, and the pumping voltage having a voltage level higher than that of the power supply voltage and the back-bias voltage having a voltage level lower than that of a ground voltage.
2. The semiconductor memory device as recited in claim 1, wherein the pre-driving unit receives the back-bias voltage as the source voltage in an active mode, and the pre-driving unit receives the ground voltage as the source voltage in an stand-by mode.
3. The semiconductor memory device as recited in claim 1, wherein the pre-driving unit includes:
a PMOS transistor connected between a terminal of the power supply voltage and an output node through which the state output signal is outputted; and
a plurality of NMOS transistors connected in series between the output node and a terminal of the source voltage,
wherein the PMOS transistor and one of the NMOS transistors receive a control signal to activate the pre-driving unit through their common gate and the remaining NMOS transistors receive the code signals through a gate thereof, respectively.
4. The semiconductor memory device as recited in claim 1, wherein the driving unit includes a PMOS transistor and an NMOS transistor which receive the pumping voltage and the back-bias voltage, respectively, through their bulk.
5. The semiconductor memory device as recited in claim 4, wherein the PMOS transistor is connected between a terminal of the power supply voltage and an output node through which the selection signal is outputted, and the NMOS transistor is connected between the output node and a terminal of the ground voltage, wherein the PMOS transistor and the NMOS transistor receive the state output signal through their common gate.
6. The semiconductor memory device as recited in claim 1, further comprising a cell matrix including a plurality of cells,
wherein the code signals contains column address information of the cells.
7. The semiconductor memory device as recited in claim 1, wherein the source voltage control unit includes:
a level shifter configured to receive and level shift a row active signal to generate an active signal, the row active signal indicating the operational mode; and
a voltage selection unit configured to provide the source voltage whose voltage level is determined in response to the active signal.
8. The semiconductor memory device as recited in claim 7, wherein the voltage selection unit includes:
an inverter configured to invert the active signal;
a first transistor connected between a terminal of the source voltage and a terminal of the ground voltage and controlled by the active signal; and
a second transistor connected between the terminal of the source voltage and a terminal of the back-bias voltage and controlled by an inverted active signal.
9. The semiconductor memory device as recited in claim 8, wherein the first transistor is turned on to provide the ground voltage to the terminal of the source voltage when the row active signal indicates a standby mode.
10. The semiconductor memory device as recited in claim 9, wherein the second transistor is turned on to provide the back-bias voltage to the terminal of the source voltage when the row active signal indicates an active mode.
11. The semiconductor memory device as recited in claim 8, wherein the voltage selection unit further includes:
a first capacitor being a parasitic capacitor which exists between the terminal of the back-bias voltage and the terminal of the ground voltage; and
a second capacitor being a parasitic capacitor which exists between the terminal of the source voltage and the terminal of the ground voltage,
wherein a capacitance of the first capacitor is greater than that of the second capacitor.
12. The semiconductor memory device as recited in claim 11, wherein the capacitance of the first capacitor is hundreds to thousands of times greater than that of the second capacitor.