1. A system for determining a velocity of a rotating device, comprising:
an apparatus having a rotational part including a set of sense magnets affixed to a rotating shaft of said rotating device configured to rotate about a rotation axis;
a circuit assembly, including a circuit interconnection having a plurality of sense coils, a sensor affixed to said circuit assembly, said circuit assembly adapted to be in proximity to said set of sense magnets;
wherein said set of sense magnets combines with said circuit assembly to form and air electric machine such that voltages generated from each sense coil of said plurality of sense coils exhibits an amplitude proportional to said velocity;
a controller coupled to said circuit assembly, said controller adapted to execute an adaptive algorithm including:
receiving a position signal related to rotational position transmitted to said controller;
determining a derived velocity signal utilizing said position signal;
receiving a plurality of tachometer velocity signals;
determining a compensated velocity signal in response to said plurality of measured tachometer velocity signals;
blending said plurality of compensated velocity signals with said derived velocity signal under selective conditions to generate a blended velocity output indicative of said velocity of said rotating device.
2. The system of claim 1 wherein said derived velocity signal is determined as a difference between two measured positions of said rotating shaft divided by a time difference between said measured positions; and filtering a resultant of said calculation.
3. The system of claim 1 wherein said plurality of tachometer velocity signals are the resultant outputs of said plurality of sense coils configured such that voltages generated thereby are in quadrature.
4. The system of claim 1 wherein said voltages generated from each sense coil of said plurality of sense coils exhibit a trapezoidal waveform with an amplitude proportional to said velocity.
5. The system of claim 1 wherein said blended velocity output is generated by combining said derived velocity signal and said compensated velocity signal under selective conditions based upon characteristics of said derived velocity signal and said plurality of tachometer velocity signals.
6. The system of claim 1 wherein:
determining said compensated velocity includes:
extracting respective offsets and biases from said plurality of tachometer velocity signals;
scaling said plurality of tachometer velocity signals to produce a plurality of scaled velocity signals;
selecting one scaled velocity signal of said plurality of scaled velocity signals as said compensated velocity signal; and
wherein said scaling is responsive to calculated velocity errors.
7. The system of claim 6 wherein said extracting is accomplished by a selectable filter.
8. The system of claim 7 wherein said selectable filter conditionally subtracts low frequency spectral components from said plurality of tachometer velocity signals.
9. The system of claim 6 wherein said scaling is applied by a scale factor multiplication, where said scale factor is derived from an error determination process.
10. The system of claim 6 wherein said selecting includes selecting one tachometer velocity signals of said plurality of tachometer velocity signals based on magnitude.
11. The system of claim 6 wherein said calculated velocity error is responsive to a magnitude differential between said derived velocity signal and a time coherent version of said compensated velocity signal.
12. A method for determining a velocity of a rotating device, comprising:
generating a plurality of tachometer velocity signals and a position signal with an apparatus comprising:
a rotational part including a set of sense magnets affixed to a rotating shaft of said rotating device configured to rotate about a rotation axis;
a circuit assembly, including a circuit interconnection having a plurality of sense coils, a sensor affixed to said circuit assembly, said circuit assembly adapted to be in proximity to said set of sense magnets; and
wherein said set of sense magnets combines with said circuit assembly to form and air electric machine such that voltages generated from each sense coil of said plurality of sense coils exhibits an amplitude proportional to said velocity;
executing an adaptive algorithm with a controller coupled to said circuit assembly, said controller:
receiving said position signal related to rotational position, and determining a derived velocity signal utilizing said position signal;
receiving said plurality of tachometer velocity signals;
determining a compensated velocity signal in response to said plurality of tachometer velocity signals; and
blending said plurality of compensated velocity signals with said derived velocity signal under selective conditions to generate a blended velocity output indicative of said velocity of said rotating device.
13. The method of claim 12 wherein said derived velocity signal is determined as a difference between two measured positions of said rotating shaft divided by a time difference between said measured positions; and filtering a resultant of said calculation.
14. The method of claim 12 wherein said plurality of tachometer velocity signals are the resultant outputs of said plurality of sense coils configured such that the voltages generated thereby are in quadrature.
15. The method of claim 12 wherein said voltages generated from each sense coil of said plurality of sense coils exhibit a trapezoidal waveform with an amplitude proportional to said velocity.
16. The method of claim 12 wherein said blended velocity output is generated by combining said derived velocity signal and said compensated velocity signal under selective conditions based upon characteristics of said derived velocity signal and said plurality tachometer velocity signals.
17. The method of claim 12 wherein:
determining said compensated velocity includes:
extracting respective offsets and biases from said plurality of tachometer velocity signals;
scaling said plurality of tachometer velocity signals to produce a plurality of scaled velocity signals;
selecting one scaled velocity signal of said plurality of scaled velocity signals as said compensated velocity signal; and
wherein said scaling is responsive to calculated velocity errors.
18. The method of claim 17 wherein said extracting is accomplished by a selectable filter.
19. The method of claim 18 wherein said selectable filter conditionally subtracts low frequency spectral components from said plurality of tachometer velocity signals.
20. The method of claim 17 wherein said scaling is applied by a scale factor multiplication, where said scale factor is derived from an error determination process.
21. The method of claim 17 wherein said selecting includes selecting one tachometer velocity signals of said plurality of tachometer velocity signals based on magnitude.
22. The method of claim 17 wherein said calculated velocity error is responsive to a magnitude differential between said derived velocity signal and a time coherent version of said compensated velocity signal.
23. A storage medium encoded with a machine-readable computer program code;
wherein said code includes instructions for causing a controller to implement a method for determining a velocity of a rotating device comprising:
generating a plurality of tachometer velocity signals and a position signal with an apparatus comprising:
a rotational part including a set of sense magnets affixed to a rotating shaft of said rotating device configured to rotate about a rotation axis;
a circuit assembly, including a circuit interconnection having a plurality of sense coils, a sensor affixed to said circuit assembly, said circuit assembly adapted to be in proximity to said set of sense magnets;
wherein said set of sense magnets combines with said circuit assembly to form and air electric machine such that voltages generated from each sense coil of said plurality of sense coils exhibits an amplitude proportional to said velocity;
executing an adaptive algorithm with a controller coupled to said circuit assembly, said controller:
receiving said position signal related to rotational position, and determining a derived velocity signal utilizing said position signal;
receiving said plurality of tachometer velocity signals;
determining a compensated velocity signal in response to said plurality of tachometer velocity signals; and
blending said plurality of compensated velocity signals with said derived velocity signal under selective conditions to generate a blended velocity output indicative of said velocity of said rotating device.
24. A storage medium of claim 23 wherein said blended velocity output is generated by combining said derived velocity signal and said compensated velocity signal under selective conditions based upon characteristics of said derived velocity signal and said plurality of tachometer velocity signals.
25. A storage medium of claim 23 wherein:
determining said compensated velocity includes:
extracting respective offsets and biases from said plurality of tachometer velocity signals;
scaling said plurality of tachometer velocity signals to produce a plurality of scaled velocity signals;
selecting one scaled velocity signal of said plurality of scaled velocity signals as said compensated velocity signal; and
wherein said scaling is responsive to calculated velocity errors.
26. A computer data signal embodied in a carrier wave;
wherein said data signal comprising code configured to cause a controller to implement a method for determining a velocity of a rotating device, comprising:
generating a plurality of tachometer velocity signals and a position signal with an apparatus comprising:
a rotational part including a set of sense magnets affixed to a rotating shaft of said rotating device configured to rotate about a rotation axis;
a circuit assembly, including a circuit interconnection having a plurality of sense coils, a sensor affixed to said circuit assembly, said circuit assembly adapted to be in proximity to said set of sense magnets;
wherein said set of sense magnets combines with said circuit assembly to form and air electric machine such that voltages generated from each sense coil of said plurality of sense coils exhibits an amplitude proportional to said velocity;
executing an adaptive algorithm with a controller coupled to said circuit assembly, said controller:
receiving said position signal related to rotational position, and determining a derived velocity signal utilizing said position signal;
receiving said plurality of tachometer velocity signals;
determining a compensated velocity signal in response to said plurality of tachometer velocity signals; and
blending said plurality of compensated velocity signals with said derived velocity signal under selective conditions to generate a blended velocity output indicative of said velocity of said rotating device.
27. A computer data signal of claim 26 wherein said blended velocity output is generated by combining said derived velocity signal and said compensated velocity signal under selective conditions based upon characteristics of said derived velocity signal and said plurality of tachometer velocity signals.
28. A computer data signal of claim 26 wherein:
determining said compensated velocity includes:
extracting respective offsets and biases from said plurality of tachometer velocity signals;
scaling said plurality of tachometer velocity signals to produce a plurality of scaled velocity signals;
selecting one scaled velocity signal of said plurality of scaled velocity signals as said compensated velocity signal; and
wherein said scaling is responsive to calculated velocity errors.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A shift register comprising:
a plurality of stages of first circuits each of which includes a circuitry, said circuitry comprising:
a first circuit comprising a first transistor and a second transistor;
a second circuit comprising a third transistor and a fourth transistor; and
a third circuit comprising a fifth transistor and a switching element,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to a first terminal of the circuitry,
wherein the other of the source and the drain of the first transistor is electrically connected to a first power source,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first power source,
wherein the other of the source and the drain of the second transistor is electrically connected to a second power source,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second power source,
wherein at least one of a gate of the third transistor and a gate of the fourth transistor is electrically connected to a second terminal,
wherein a first terminal of the switching element is input with a clock signal,
wherein a second terminal of the switching element is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a third terminal,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to a fourth terminal, and
wherein a third terminal of the switching element is electrically connected to a fifth terminal.
2. The shift register according to claim 1,
wherein the first transistor and the fourth transistor are p-channel transistors and the third transistor and the fifth transistor are n-channel transistors.
3. The shift register according to claim 1,
wherein the first power source supplies a higher power source potential than the second power source to the one of the source and the drain of the first transistor and the one of the source and the drain of the fourth transistor.
4. A shift register comprising:
a plurality of stages of flip-flop circuits each of which includes a clocked inverter, said clocked inverter comprising:
an inverter comprising a first transistor and a second transistor;
a first compensation circuit comprising a third transistor and a fourth transistor; and
a second compensation circuit comprising a fifth transistor and a switching element,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to an output terminal of the clocked inverter,
wherein the other of the source and the drain of the first transistor is electrically connected to a first power source,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first power source,
wherein the other of the source and the drain of the second transistor is electrically connected to a second power source,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second power source,
wherein at least one of a gate of the third transistor and a gate of the fourth transistor is inputted with a signal outputted from the clocked inverter used in the flip-flop circuit of the preceding stage,
wherein a gate of the fifth transistor is inputted with a signal outputted from the flip-flop circuit of a succeeding stage,
wherein an input terminal of the switching element is inputted with a clock signal,
wherein an output terminal of the switching element is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the third transistor is inputted with a signal outputted from the clocked inverter used in the flip-flop circuit of two stages before,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor, and
wherein the other of the source and the drain of the fourth transistor are connected to a gate of the first transistor.
5. The shift register according to claim 4,
wherein the first transistor and the fourth transistor are p-channel transistors and the third transistor and the fifth transistor are n-channel transistors.
6. The shift register according to claim 4,
wherein the first power source supplies a higher power source potential than the second power source to the source of the first transistor and the source of the fourth transistor.
7. A shift register comprising:
a plurality of stages of flip-flop circuits each of which includes a clocked inverter, said clocked inverter comprising:
an inverter comprising a first transistor and a second transistor;
a first compensation circuit comprising a third transistor and a fourth transistor; and
a second compensation circuit comprising a fifth transistor and a switching element,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to an output terminal of the clocked inverter,
wherein the other of the source and the drain of the first transistor is electrically connected to a first power source,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first power source,
wherein the other of the source and the drain of the second transistor is electrically connected to a second power source,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second power source,
wherein at least one of a gate of the third transistor and a gate of the fourth transistor is inputted with a signal outputted from the clocked inverter used in the flip-flop circuit of the preceding stage,
wherein a gate of the fifth transistor is inputted with a signal outputted from the flip-flop circuit of a succeeding stage,
wherein an input terminal of the switching element is inputted with a clock signal,
wherein an output terminal of the switching element is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the third transistor is inputted with a signal outputted from the clocked inverter used in the flip-flop circuit of two stages before,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor, and
wherein the other of the source and the drain of the fourth transistor are connected to a gate of the second transistor.
8. The shift register according to claim 7,
wherein the first transistor, the third transistor, and the fifth transistor are p-channel transistors and the second transistor and the fourth transistor are n-channel transistors.
9. The shift register according to claim 7,
wherein the first power source supplies a higher power source potential than the second power source to the source of the first transistor and the source of the fifth transistor.