What is claimed is:
1. A process for measuring antibodies, antigens and small molecules by using mono- and poly-clonal antibody-based micro- and micro-array technology, comprising the steps of:
(a) creating a reactant by adsorbing a first set of specific (capture) antibodies into a well of a plastic microtiter plate;
(b) adding a test solution into said well;
(c) incubating said test solution with said reactant;
(d) washing out a group of unbound antigens from said test solution with said reactant;
(e) incubating said test solution with said reactant without said unbound antigens;
(f) adding a second set of antibodies that is specific for conjugating to an enzyme;
(g) washing out a set of unbound conjugates from said test solution with said reactant;
(h) adding a detecting agent to said plate that is specific for a substrate formed from said enzymes; and
(i) detecting said detecting agent for determining a quantity of said substrate.
2. A process for measuring antibodies, antigens and small molecules by using mono- and poly-clonal antibody-based micro- and micro-array technology, comprising the steps of:
(a) creating a reactant by adsorbing a first set of specific (capture) antibodies onto a glass slide;
(b) adding a test solution onto said slide;
(c) incubating said test solution with said reactant;
(d) washing out a group of unbound antigens from said test solution with said reactant;
(e) incubating said test solution with said reactant without said unbound antigens;
(f) adding a second set of antibodies that is specific for conjugating to an enzyme;
(g) washing out a set of unbound conjugates from said test solution with said reactant;
(h) adding a detecting agent to said slide that is specific for a substrate formed from said enzymes; and
(i) detecting said detecting agent for determining a quantity of said substrate.
3. A process for measuring antibodies, antigens and small molecules by using mono- and poly-clonal antibody-based micro- and micro-array technology, comprising the steps of:
(a) creating a reactant by adsorbing a first set of specific (capture) antibodies into a well of a filter (membrane);
(b) adding a test solution into said filter;
(c) incubating said test solution with said reactant;
(d) washing out a group of unbound antigens from said test solution with said reactant;
(e) incubating said test solution with said reactant without said unbound antigens;
(f) adding a second set of antibodies that is specific for conjugating to an enzyme;
(g) washing out a set of unbound conjugates from said test solution with said reactant;
(h) adding a detecting agent to said filter that is specific for a substrate formed from said enzymes; and
(i) detecting said detecting agent for determining a quantity of said substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory interface circuit comprising:
a memory bus arbitrating circuit having a refresh request signal and other processing request signals input thereto, and which selects from among the request signals simultaneously-inputted thereto a request signal with a highest priority;
a memory controlling circuit for controlling a main memory on the basis of said request signal selected by said memory bus arbitrating circuit;
a counting circuit for counting a timing for refreshing said main memory; and
a monitoring circuit for outputting said refresh request signal based on a result of comparing a count value of said counting circuit against a comparison value stored in an overwrite-capable memory, said monitoring circuit comprises
a first overwrite-capable memory for storing a first comparison value inputted from outside,
a second overwrite-capable memory for storing a second comparison value inputted from outside,
a first comparing circuit for outputting a first signal when the count value of said counting circuit either matches or exceeds said first comparison value,
a second comparing circuit for outputting a second signal when the count value of said counting circuit either matches or exceeds said second comparison value, and
a gate circuit for outputting said refresh request signal from an output timing of said first signal to an output timing of said second signal.
2. The memory interface circuit according to claim 1, wherein said gate circuit is an AND gate.
3. The memory interface circuit according to claim 1, wherein each of the request signals input to said memory bus arbitrating circuit has different priority, and the priority of said refresh request signal is higher than that of the other processing request signals.
4. The memory interface circuit according to claim 1, wherein said counting circuit counts a time cyclically with a predetermined cycle.
5. The memory interface circuit according to claim 1, wherein said first and second overwrite-capable memories respectively store the first and second comparison values in overwritable states.
6. A memory interface circuit comprising:
a memory bus arbitrating circuit having a refresh request signal and other processing request signals input thereto, and which selects from among the request signals simultaneously-inputted thereto a request signal with a highest priority;
a memory controlling circuit for controlling a main memory on the basis of said request signal selected by said memory bus arbitrating circuit;
a counting circuit for counting a timing for refreshing said main memory; and
a monitoring circuit for outputting said refresh request signal based on a result of comparing a count value of said counting circuit against a comparison value stored in an overwrite-capable memory, wherein said monitoring circuit comprises
a first overwrite-capable memory for storing said count value as a first comparison value when said memory controlling circuit starts a prescribed processing corresponding to the other processing request signals,
a second overwrite-capable memory for storing said count value as a second comparison value when said memory controlling circuit terminates said prescribed processing,
a first comparing circuit for outputting a first signal when the count value of said counting circuit either matches or exceeds said first comparison value,
a second comparing circuit for outputting a second signal when the count value of said counting circuit either matches or exceeds said second comparison value, and
a gate circuit for prohibiting output of said refresh request signal from an output timing of said first signal to an output timing of said second signal.
7. The memory interface circuit according to claim 6, wherein said gate circuit is an OR gate.
8. The memory interface circuit according to claim 6, wherein said memory controlling circuit resets the counted time of said counting circuit when said main memory is refreshed based on said refresh request signals.
9. The memory interface circuit according to claim 6, wherein each of the request signals input to said memory bus arbitrating circuit has different priority, and the priority of said refresh request signal is higher than that of the other processing request signals.
10. The memory interface circuit according to claim 6, wherein said first and second overwrite-capable memories respectively store the first and second comparison values in overwritable states.