1. A latch inverter, comprising:
a first transistor, the gate of the first transistor receiving a data signal and the source of the first transistor connected to a voltage source;
a second transistor, the gate of the second transistor receiving a first trigger clock and the source of the second transistor connected to the drain of the first transistor;
a third transistor, the gate of the third transistor receiving a second trigger clock and the drain of the third transistor connected to the drain of the second transistor to generate an output signal;
a fourth transistor, the gate of the fourth transistor receiving the data signal, the drain of the fourth transistor connected to the source of the third transistor, and the source of the fourth transistor being grounded;
a first level-adjusting unit connected to the source of the second transistor to provide the second transistor with a first voltage level; and
a second level-adjusting unit connected to the drain of the fourth transistor to provide the fourth transistor with a second voltage level.
2. The latch inverter as claimed in claim 1, wherein the second trigger clock is the inverted signal of the first trigger clock.
3. The latch inverter as claimed in claim 1, wherein the first and the second transistors are PMOS transistors, and the third and the fourth transistors are NMOS transistors.
4. The latch inverter as claimed in claim 1, wherein the first voltage level is changed to L by the first level-adjusting unit when the voltage level of the data signal is H.
5. The latch inverter as claimed in claim 4, wherein the first level-adjusting unit includes a fifth transistor, the gate of the fifth transistor receiving the data signal, the drain of the fifth transistor connected to the source of the second transistor, and the source of the fifth transistor being grounded.
6. The latch inverter as claimed in claim 5, wherein the fifth transistor is a NMOS transistor.
7. The latch inverter as claimed in claim 1, wherein the second voltage level is changed to H by the second level-adjusting unit when the voltage level of the data signal is L.
8. The latch inverter as claimed in claim 7, wherein the second level-adjusting unit includes a sixth transistor, the gate of the sixth transistor receiving the data signal, the source of the sixth transistor connected to a voltage source, and the drain of the sixth transistor connected to the drain of the fourth transistor.
9. The latch inverter as claimed in claim 8, wherein the sixth transistor is a PMOS transistor.
10. The latch inverter as claimed in claim 1, wherein the latch inverter is applied to a flip-flop.
11. The latch inverter as claimed in claim 1, wherein the latch inverter is applied to a double latch data flip-flop.
12. A flip-flop, comprising:
a first latch inverter for receiving a data signal and a trigger clock and generating a first latch signal; and
a second latch inverter for receiving the first latch signal and the trigger clock and generating a second latch signal, the second latch inverter comprising:
a first transistor, the gate of the first transistor receiving the first latch signal and the source of the first transistor connected to a voltage source;
a second transistor, the gate of the second transistor receiving the trigger clock and the source of the second transistor connected to the drain of the first transistor;
a third transistor, the gate of the third transistor receiving an inverted signal of the trigger clock and the drain of the third transistor connected to the drain of the second transistor to generate the second latch signal;
a fourth transistor, the gate of the fourth transistor receiving the first latch signal, the drain of the fourth transistor connected to the source of the third transistor, and the source of the fourth transistor being grounded;
a first level-adjusting unit for providing the second transistor with a first voltage level via the source of the second transistor; and
a second level-adjusting unit for providing the fourth transistor with a second voltage level via the drain of the fourth transistor.
13. The flip-flop as claimed in claim 12, wherein the first and the second transistors are PMOS transistors, and the third and the fourth transistors are NMOS transistors.
14. The flip-flop as claimed in claim 12, wherein the first level-adjusting unit includes a fifth transistor, the gate of the fifth transistor receiving the first latch signal, the drain of the fifth transistor connected to the source of the second transistor, and the source of the fifth transistor being grounded.
15. The flip-flop as claimed in claim 14, wherein the fifth transistor is a NMOS transistor.
16. The flip-flop as claimed in claim 12, wherein the second level-adjusting unit includes a sixth transistor, the gate of the sixth transistor receiving the first latch signal, the source of the sixth transistor connected to a voltage source, and the drain of the sixth transistor connected to the drain of the second transistor.
17. The flip-flop as claimed in claim 16, wherein the sixth transistor is a PMOS transistor.
18. A double latch data flip-flop, comprising:
a first latch inverter for receiving a first data signal and generating a first latch signal;
a first level-adjusting unit for outputting a first voltage level;
a second latch inverter for receiving the first latch signal and the first voltage level and generating a second latch signal, wherein the response speed of the second latch signal is elevated as a result of the first voltage level;
a third latch inverter for receiving a second data signal and generating a third latch signal;
a second level-adjusting unit for outputting a second voltage level;
a fourth latch inverter for receiving the third latch signal and the second voltage level and generating a fourth latch signal, wherein the response speed of the fourth latch signal is elevated as a result of the second voltage level; and
a buffer for receiving the third and the fourth latch signals and generating an output signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A compound of formula I:
wherein R1 and R2 are each independently selected from H, OH or OPR;
R3 and R4 are each independently selected from H, OH, OPR, \u2550O, cyano, substituted or unsubstituted alkyl, substituted or unsubstituted aryl, substituted or unsubstituted heterocyclyl, substituted or unsubstituted alkoxy, substituted or unsubstituted aryloxy, substituted or unsubstituted amino or halogen,
R5 and R6 together are \u2550O or \u2014O\u2014(CH2)m\u2014, wherein m is selected from 1, 2, 3, 4 or 5; or R5 is selected from H. OH, or OPR. and R6 is selected from hydrogen, cyano, substituted or unsubstituted alkyl, substituted or unsubstituted cycloalkyl, substituted or unsubstituted alkenyl, substituted or unsubstituted alkynyl, substituted or unsubstituted aryl, substituted or unsubstituted heterocyclyl,
with the proviso that at least one of R1, R2, R3, R4 or R5 is OH or OPR; PR is an hydroxyl protecting group which can be the same or different on each of R1, R2, R3, R4 or R5;
the dotted line represents a single or double bond, with the proviso that when both R1 and R2 or R3 and R4 are H then there is a double bond between the two C to which the H are linked;
Z is \u2014CRaRb)n\u2014 wherein n is a number selected from 1, 2 or 3 and Ra and Rb are each independently selected from hydrogen, substituted or unsubstituted alkyl, substituted or unsubstituted cycloalkyl, substituted or unsubstituted alkenyl, substituted or unsubstituted aryl, substituted or unsubstituted heterocyclyl, substituted or unsubstituted alkoxy, substituted or unsubstituted aryloxy, substituted or unsubstituted amino or halogen;
Y is selected from \u2014O\u2014, \u2014S\u2014, \u2014N(RaRb)\u2014 or \u2014C(O)\u2014, wherein Ra and Rb are as previously defined and do not form a cyclic ring;
W is a group selected from substituted or unsubstituted arylalkyl, substituted or unsubstituted heterocyclylalkyl, substituted or unsubstituted alkenyl;
or a salt, complex or solvate thereof.
2. A compound according to claim 1 characterized in that Z is -(CHRa)n\u2014 , Ra and n being as defined in claim 1.
3. A compound according to claim 1 characterized in that n is 1.
4. A compound according to claim 1 characterized in that Y is \u2014O\u2014.
5. A compound as defined in claim 1 characterized in that W is \u2014CRaRb-Q, wherein Ra and Rb are as previously defined and Q is substituted or unsubstituted aryl, substituted or usubstituted heterocyclyl, substituted or unsubstituted alkenyl.
6. A compound according to claim 1 which corresponds to any of the following formulae:
wherein Z, Y and W are as defined in claim 1; PR1 to PR5 are hydroxyl protecting groups which can be independently the same or different on each hydroxyl and can optionally protect at the same time two hydroxyl groups, and Nu is a nucleophilic group; their diastereoisomers, enantiomers and mixtures thereof.
7. A process for the preparation of a compound according to claim 1 which comprises in any order one or more of a step selected from the group consisting of:
a) hydroxylation or dihydroxylation
b) hydroxyl or carbonyl protection
c) nucleophilic attack on the carbonyl group
d) hydroxyl inversion
e) allylic rearrangement
applied to a compound of formula IV:
wherein Z , Y and W are as defined in claim 1.
8. A compound according to claim 2 characterized in that n is 1.
9. A compound according to claim 2 characterized in that Y is \u2014O\u2014.
10. A compound according to claim 3 characterized in that Y is \u2014O\u2014.
11. A compound according to claim 8 characterized in that Y is \u2014O\u2014.
12. A compound as defined in claim 2 characterized in that W is \u2014CRaRb-Q, wherein Ra and Rb are as previously defined and Q is substituted or unsubstituted aryl, substituted or usubstituted heterocyclyl, substituted or unsubstituted alkenyl.
13. A compound as defined in claim 3 characterized in that W is \u2014CRaRb-Q, wherein Ra and Rb are as previously defined and Q is substituted or unsubstituted aryl, substituted or usubstituted heterocyclyl, substituted or unsubstituted alkenyl.
14. A compound as defined in claim 4 characterized in that W is \u2014CRaRb-Q, wherein Ra and Rb are as previously defined and Q is substituted or unsubstituted aryl, substituted or usubstituted heterocyclyl, substituted or unsubstituted alkenyl.
15. A compound as defined in claim 8 characterized in that W is \u2014CRaRb-Q, wherein Ra and Rb are as previously defined and Q is substituted or unsubstituted aryl, substituted or usubstituted heterocyclyl, substituted or unsubstituted alkenyl.
16. A compound as defined in claim 9 characterized in that W is \u2014CRaRb-Q, wherein Ra and Rb are as previously defined and Q is substituted or unsubstituted aryl, substituted or usubstituted heterocyclyl, substituted or unsubstituted alkenyl.
17. A compound as defined in claim 10 characterized in that W is \u2014CRaRb-Q, wherein Ra and Rb are as previously defined and Q is substituted or unsubstituted aryl, substituted or usubstituted heterocyclyl, substituted or unsubstituted alkenyl.
18. A compound as defined in claim 1 1 characterized in that W is CRaRb-Q, wherein Ra and Rb are as previously defined and Q is substituted or unsubstituted aryl, substituted or usubstituted heterocyclyl, substituted or unsubstituted alkenyl.