What is claimed is:
1. A memory card for use with a host device, comprising:
a) a one-time programmable memory having locations for storing a plurality of storage allocation tables, data files identified by the storage allocation tables, and a translation table; and
b) a controller for enabling the host device to access the one-time programmable memory and to modify the data files, wherein the controller:
i) stores initial data files, a first storage allocation table, and an initial translation table in the one-time programmable memory;
ii) accesses the translation table in the one-time programmable memory to identify the physical location of the first storage allocation table and returns such storage allocation table to the host device for subsequent accessing of the initial data files,
iii) nables the host device to modify at least one of the initial data files
iv) stores a second storage allocation table, different from the first storage allocation table, in the one-time programmable memory to enable the host device to access the modified data files;
v) amends the translation table to indicate the location of the second storage allocation table, wherein the amended traslation table includes a plurality of entries with the latest entry corrsesponding to the location of the latest storage allocation table in the one-time programmable memory, and the latest entry is the latest noninitialized entry; and
vi) accesses the amended translator table to identify the physical location of the second storage allocation table and returning such second storage allocation table to the host device to enable access of the modified data files.
2. The memory card of claim 1 wherein the storage allocation tables are file allocation tables.
3. The memory card of claim 1 wherein the data files include images.
4. The memory card of claim 1 wherein the host device is a digital camera.
5. The memory card of claim 1 wherein the host device is a personal computer.
6. The memory card of claim 1 wherein data stored in the storage allocation table is logically inverted as it is written into the one-time programmable memory.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer system, comprising:
at least one processor; and
a main memory, communicatively coupled to the at least one processor, comprising:
a non-volatile memory; and
a volatile memory,
wherein the main memory includes a contiguous range of real addresses supported by the non-volatile memory and the volatile memory, the non-volatile memory is capable of containing data for every address in the contiguous range of real addresses, and the volatile memory is capable of containing data for at least a subset of the contiguous range of real addresses.
2. The computer system of claim 1, wherein the main memory includes at least one additional contiguous range of real addresses supported by the non-volatile memory and the volatile memory.
3. The computer system of claim 1, wherein the volatile memory is configured as a cache for the non-volatile memory.
4. The computer system of claim 3, wherein the cache is configured to retain data contained in at least one pinned address.
5. The computer system of claim 1, wherein the main memory further comprises a compression unit communicatively coupled to the non-volatile memory, the compression unit configured to compress data written to the non-volatile memory and decompress data read from the non-volatile memory.
6. The computer system of claim 1, wherein the main memory further comprises an encryption unit communicatively coupled to the non-volatile memory, the encryption unit configured to encrypt data written to the non-volatile memory and decrypt data read from the non-volatile memory.
7. The computer system of claim 1, wherein at least a subset of the non-volatile memory is configured to contain a system image.
8. The computer system of claim 1, wherein at least a subset of the non-volatile memory is configured to contain an emulated disk image managed by an operating system.
9. The computer system of claim 1, wherein at least a subset of the non-volatile memory is configured as a data region for containing a page-file managed by an operating system.
10. The computer system of claim 1, wherein the main memory further comprises:
at least one pluggable memory module, comprising:
a printed circuit board;
a pluggable connector, coupled to the printed circuit board;
at least a portion of the volatile memory, coupled to the printed circuit board;
at least a portion of the nonvolatile memory, coupled to the printed circuit board;
a module controller coupled to the printed circuit board and communicatively coupled to the pluggable connector, the at least a portion of the volatile memory, and the at least a portion of the nonvolatile memory.
11. The computer system of claim 1, wherein the main memory further comprises:
a main memory controller;
at least one volatile pluggable memory module, communicatively coupled to the main memory controller, comprising:
a printed circuit board;
a pluggable connector, coupled to the printed circuit board; and
at least a portion of the volatile memory, communicatively coupled to the pluggable connector; and
at least one non-volatile pluggable memory module, communicatively coupled to the main memory controller, comprising:
a printed circuit board;
a pluggable connector, coupled to the printed circuit board; and
at least a portion of the non-volatile memory, communicatively coupled to the pluggable connector.
12. A main memory for a computer system, comprising:
a memory controller, including an interface configured to communicate with a processor of the computer system;
volatile memory, communicatively coupled to the main memory controller, including at least one volatile pluggable memory module, comprising:
a printed circuit board;
a pluggable connector, coupled to the printed circuit board; and
at least a portion of the volatile memory, communicatively coupled to the pluggable connector; and
non-volatile memory, communicatively coupled to the main memory controller, including at least one non-volatile pluggable memory module comprising:
a printed circuit board;
a pluggable connector, coupled to the printed circuit board; and
at least a portion of the non-volatile memory, communicatively coupled to the pluggable connector,
wherein the main memory includes a contiguous range of real addresses supported by the non-volatile memory and the volatile memory, the non-volatile memory is capable of containing data for every address in the contiguous range of real addresses, and the volatile memory is capable of containing data for at least a subset of the contiguous range of real addresses.
13. The main memory for a computer system of claim 12, wherein the memory controller is configured to utilize the volatile memory as a cache for the non-volatile memory.
14. The main memory for a computer system of claim 13, wherein the cache is configured to retain data contained in at least one pinned address.
15. The main memory for a computer system of claim 12, wherein the memory controller further comprises a compression unit communicatively coupled to the non-volatile memory, the compression unit configured to compress data written to the non-volatile memory and decompress data read from the non-volatile memory.
16. The main memory for a computer system of claim 12, wherein the memory controller further comprises an encryption unit communicatively coupled to the non-volatile memory, the encryption unit configured to encrypt data written to the non-volatile memory and decrypt data read from the non-volatile memory.
17. The main memory for a computer system of claim 12, wherein the non-volatile memory comprises NAND flash memory.
18. The main memory for a computer system of claim 12, wherein the volatile memory comprises dynamic random access memory (DRAM).
19. A main memory module for a computer system, comprising:
a printed circuit board;
a pluggable connector, coupled to the printed circuit board;
a volatile memory, coupled to the printed circuit board;
a nonvolatile memory, coupled to the printed circuit board;
a module controller coupled to the printed circuit board and communicatively coupled to the pluggable connector, the volatile memory, and the nonvolatile memory;
wherein the volatile memory and the non-volatile memory support at least one contiguous range of real addresses for a main memory of the computer system.
20. The main memory module of claim 19, wherein the module controller is configured to utilize the volatile memory as a cache for the non-volatile memory.
21. The main memory module of claim 20, wherein the cache is configured to retain data contained in at least one pinned address.
22. The main memory module of claim 19, wherein the module controller further comprises a compression unit communicatively coupled to the non-volatile memory, the compression unit configured to compress data written to the non-volatile memory and decompress data read from the non-volatile memory.
23. The main memory module of claim 19, wherein the module controller further comprises an encryption unit communicatively coupled to the non-volatile memory, the encryption unit configured to encrypt data written to the non-volatile memory and decrypt data read from the non-volatile memory.
24. The main memory module of claim 19, wherein the non-volatile memory comprises NAND flash memory.
25. The main memory module of claim 19, wherein the volatile memory comprises dynamic random access memory (DRAM).