1. Fuel cell comprising a solid electrolyte layer (12) and two electrode layers (11, 13) which are applied by means of coating procedures to an open pored, electrically conducting carrier structure (10) in the sequence anode (11), electrolyte (12) and cathode (13) and form a plate-like multiple layer system (1), with this multiple layer plate (1) having an outer edge which is exposed during a current generating operation of the fuel cell to an external environment (60) which contains molecular oxygen and with the material of the carrier structure assuming an oxidized or a reduced state in thermodynamical equilibrium at the operating temperature of the fuel cell depending on the environment, characterized in that the outer edge (16) of the multiple layer plate is covered over with an inert material; and in that this edge covering (122, 126) forms at the operating temperature of the fuel cell a barrier which inhibits or prevents the transport of molecular oxygen out of the external environment (60) into the carrier structure, with the inert material of the edge covering being zirconium dioxide ZrO2 which is stabilized with yttrium oxide Y2O3.
2. Fuel cell in accordance with claim 1, characterized by a carrier structure (10) which permits a transition from the oxidized into the reduced state, in which in spite of a density reduction no macroscopic fissures develop as long as the transition takes place homogeneously over the entire carrier structure.
3. Fuel cell in accordance with claim 1, characterized by a carrier structure (10) which is manufactured of the same material as that of the anode (11), with the material being a mixture of metal or metal oxide respectively and ceramic material, and with the metal being Ni or the metal oxide being NiO respectively and with the ceramic material being one of the following substances or a mixture of these substances: YSZ, Al2O3, TiO2, MgAl2O4, LaCrO3 or doped CeO2, which is doped with Gd oxide, Sm oxide, Ca oxide or Y oxide.
4. Fuel cell in accordance with claim 1, characterized by a carrier structure (10), the porosity of which has a value in the range between 20 and 35% in the oxidized state, the pore diameters of which have values which are largely distributed over a range from 1 to 10 \u03bcm, the thickness of which is greater than 0.3 mm and less than 1.2 mm.
5. Fuel cell in accordance with claim 1, characterized in that the edge covering (122, 126) is applied by means of spraying on of a slurry-like material, immersion into a material of this kind, transfer of the material with intermediate carriers or silk screen printing.
6. Fuel cell in accordance with claim 5, characterized in that the electrolyte layer (12) and the edge covering (122, 126) are applied using a single material forming a connected layer; or in that the electrolyte layer (12) and the edge covering (122, 126) are each applied in a separate layer, with the material for the edge covering being YSZ, TiO2, Al2O3, MgAl2O4, LaCrO3 or a mixture of these substances.
7. Fuel cell in accordance with claim 1, characterized in that the outer edge (16\u2032) of the carrier structure (10) has the shape of a circle or a curve (16\u2033) lying between two concentric circles (160, 161), with this boundary curve (16\u2033) having a periodic pattern along the periphery, for example radially directed indentations, grooves or clefts (162), or comprises a fringe of apertures which are at least partly filled by the material of the edge covering.
8. Fuel cell in accordance with claim 1, characterized in that the carrier structure (10) is covered over on a lateral surface (122\u2032) by the edge covering, with the lateral surface extending parallel to the layers of the multiple layer system (1) and the edge covering (122) being restricted to a boundary zone in which no electrochemical processes take place in the current generating operation.
9. Battery with fuel cells in accordance with claim 1, characterized in that the multiple layer plates (1) and interconnectors (2) are put together in an alternating arrangement to form a stack of cells (3); in that a ring space (6) with one or more afterburner chambers is provided at the lateral surface of the cell stack; and in that the ring space forms the environment (60) of the cell containing the oxygen during a current generating operation.
10. Fuel cell comprising a solid electrolyte layer and first and second electrode layers coated onto an open-pored, electrically conducting carrier structure in the sequence anode, electrolyte and cathode to form a multiple layer plate which has an outer edge which is exposed during a current generating operation of the fuel cell to an external environment that includes molecular oxygen, the material of the carrier structure assuming an oxidized or a reduced state in thermodynamic equilibrium at the operating temperature of the fuel cell, the outer edge of the multiple layer plate being coated by an inert material that forms at an operating temperature of the fuel cell a barrier inhibiting transportation of molecular oxygen from the external environment into the carrier structure.
11. Fuel cell in accordance with claim 10, wherein the inert material covering the outer edge comprises zirconium dioxide ZrO2 which is stabilized with yttrium oxide Y2O3.
12. Fuel cell in accordance with claim 10, wherein the carrier structure is manufactured of the same material as that of the anode and comprises a mixture of one of metal and metal oxide and a ceramic material.
13. Fuel cell in accordance with claim 10, wherein the electrolyte layer and the edge covering are one of applied using a single material forming a connected layer and applied as separate layers.
14. Fuel cell in accordance with claim 10, wherein the outer edge of the carrier structure has a shape of one of a circle and a curve lying between two concentric circles.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A nonvolatile semiconductor memory device comprising:
a substrate;
a semiconductor region formed in an upper portion of the substrate;
a plurality of dielectric films and electrode films which are alternately stacked on the substrate and have a plurality of through holes extending in the stacking direction and formed in a matrix configuration as viewed along the stacking direction;
conductor pillars buried inside a subset of the plurality of through holes, piercing at least one of the dielectric films and at least one of the electrode films, the through holes in the subset being arranged in a first direction;
semiconductor pillars buried inside the remaining through holes, piercing the dielectric films and the electrode films, and connected to the semiconductor region;
a shunt interconnect provided above the plurality of dielectric films and electrode films and connected to the conductor pillars;
a bit interconnect provided above the plurality of dielectric films and electrode films and connected to the semiconductor pillars;
a charge storage layer provided at least between one of the semiconductor pillars and some of the electrode films,
the conductor pillars having a lower resistivity than the semiconductor pillars, and
the conductor pillars being connected to one of the electrode films, and not connected to the other electrode films and the semiconductor region.
2. The memory device according to claim 1, wherein the conductor pillars are connected to the lowermost one of the electrode films.
3. The memory device according to claim 1, wherein the conductor pillars are connected to one of the electrode films other than the uppermost and lowermost one of the electrode films.
4. The memory device according to claim 1, further comprising:
an upper interconnect provided above the shunt interconnect and the bit interconnect, extending in a second direction crossing the first direction, and connected to the shunt interconnect.
5. The memory device according to claim 4, wherein the upper interconnect is connected to the semiconductor region.
6. The memory device according to claim 4, wherein the conductor pillars are connected to the lowermost one of the electrode films.
7. A nonvolatile semiconductor memory device comprising:
a substrate;
a semiconductor region formed in an upper portion of the substrate;
a plurality of dielectric films and electrode films which are alternately stacked on the substrate and have a plurality of through holes extending in the stacking direction and formed in a matrix configuration as viewed along the stacking direction;
conductor pillars buried inside a subset of the plurality of through holes, piercing at least one of the dielectric films and at least one of the electrode films, the through holes in the subset being arranged in a first direction;
semiconductor pillars buried inside the remaining through holes, piercing the dielectric films and the electrode films, and connected to the semiconductor region;
a shunt interconnect provided above the plurality of dielectric films and electrode films and connected to the conductor pillars;
a bit interconnect provided above the plurality of dielectric films and electrode films and connected to the semiconductor pillars;
an upper interconnect provided above the shunt interconnect and the bit interconnect, extending in a second direction crossing the first direction, and connected to the shunt interconnect; and
a charge storage layer provided at least between one of the semiconductor pillars and some of the electrode films,
the conductor pillars having a lower resistivity than the semiconductor pillars,
the conductor pillars being connected to the semiconductor region, and not connected to the electrode films,
the semiconductor region being divided into a plurality of portions arranged along the first direction and separated from each other, and
the shunt interconnect and the upper interconnect being provided for each of the portions.