1. A Hall-effect apparatus having a complementary structure comprising; an n-type epitaxial Hall element, wherein said n-type epitaxial Hall element comprises a first pair of sensing contacts disposed on a substrate layer, said n-type epitaxial Hall element surrounded vertically by an isolation layer;
a p-type Hall element comprising a second pair of sensing contacts implanted on a region of said n-type epitaxial layer isolated from said n-type epitaxial Hall element, wherein said n-type epitaxial Hall element and said p-type Hall element are biased in a parallel arrangement in order to provide similar quiescent output voltages thereof; and
an insulation layer associated with a plurality of conductors disposed above said n-type epitaxial Hall element and said p-type Hall element, thereby geometrically connecting said second pair of sensing contacts to said first pair of sensing contacts through a resistive network and providing an output signal thereof through said first pair of sensing contacts.
2. The apparatus of claim 1 wherein said n-type epitaxial Hall element and said p-type Hall element comprise a pair of electrical bias contacts.
3. The apparatus of claim 1 wherein said n-type epitaxial Hall element is arranged in a non-merged configuration with respect to said p-type Hall element.
4. The apparatus of claim 1 wherein said resistive network is configured to restrict variation in a magnitude of said output signal in response to temperature changes.
5. The apparatus of claim 1 wherein said output signal comprises a voltage signal indicative of said n-type epitaxial Hall element.
6. The apparatus of claim 1 wherein said n-type epitaxial Hall element and said p-type Hall element are configured on a semiconductor body comprising silicon and utilizing a silicon integrated circuit technology.
7. A Hall-effect apparatus having a merged complementary structure, comprising;
an n-type epitaxial Hall element comprising a first pair of sensing contacts disposed on a substrate layer, wherein said n-type epitaxial Hall element is surrounded vertically by an isolation layer;
a p-type Hall element comprising a second pair of sensing contacts implanted directly on said n-type epitaxial Hall element, wherein said n-type epitaxial Hall element and said p-type Hall element are biased in a parallel arrangement in order to provide a zero-bias depletion layer throughout for isolation; and
an insulation layer associated with a plurality of conductors disposed above said p-type Hall element thereby geometrically connecting said second pair of sensing contacts to geometrically corresponding said first pair of sensing contacts through a suitable resistive network and taking an output signal through said first pair of sensing contacts.
8. The apparatus of claim 7 wherein said n-type epitaxial Hall element and said p-type Hall element comprise a pair of electrical bias contacts.
9. The apparatus of claim 7 wherein said n-type epitaxial Hall element is merged with said p-type Hall element so that an individual stress-induced offset is associated with destructively combining the offsets of said n-type epitaxial Hall element and said p-type Hall element.
10. The apparatus of claim 7 wherein said resistive network is configured to restrict a variation in a magnitude of said output signal in response to temperature changes.
11. The apparatus of claim 7 wherein said output signal comprises a voltage signal indicative of said n-type epitaxial Hall element.
12. The apparatus of claim 7 wherein said n-type epitaxial Hall element and said p-type Hall element are configured on a semiconductor body comprising silicon and utilizing a silicon integrated circuit technology.
13. The apparatus of claim 7 wherein:
said n-type epitaxial Hall element and said p-type Hall element comprise a pair of electrical bias contacts;
said n-type epitaxial Hall element is merged with said p-type Hall element so that an individual stress-induced offset is associated with destructively combining the offsets of said n-type epitaxial Hall element and said p-type Hall element; and
said resistive network is configured to restrict a variation in a magnitude of said output signal in response to temperature changes.
14. The apparatus of claim 13 wherein said output signal comprises a voltage signal indicative of said n-type epitaxial Hall element and wherein said n-type epitaxial Hall element and said p-type Hall element are configured on a semiconductor body comprising silicon and utilizing a silicon integrated circuit technology.
15. A method of configuring a Hall-effect apparatus to comprise a merged complementary structure, comprising;
configuring an n-type epitaxial Hall element to comprise a first pair of sensing contacts disposed on a substrate layer;
surrounding said n-type epitaxial Hall element vertically by an isolation layer;
configuring a p-type Hall element to comprise a second pair of sensing contacts implanted directly on said n-type epitaxial Hall element, such that said n-type epitaxial Hall element and said p-type Hall element are biased in a parallel arrangement in order to provide a zero-bias depletion layer throughout for isolation; and
associating an insulation layer with a plurality of conductors disposed above said p-type Hall element thereby geometrically connecting said second pair of sensing contacts to geometrically corresponding said first pair of sensing contacts through a suitable resistive network and taking an output signal through said first pair of sensing contacts.
16. The method of claim 15 wherein said n-type epitaxial Hall element and said p-type Hall element comprise a pair of electrical bias contacts.
17. The method of claim 15 further comprising merging said n-type epitaxial Hall element with said p-type Hall element so that an individual stress-induced offset is associated with destructively combining the offsets of said n-type epitaxial Hall element and said p-type Hall element.
18. The method of claim 15 further comprising configuring said resistive network to restrict a variation in a magnitude of said output signal in response to temperature changes.
19. The method of claim 15 further comprising modifying said output signal to comprise a voltage signal indicative of said n-type epitaxial Hall element.
20. The method of claim 15 further comprising configuring said n-type epitaxial Hall element and said p-type Hall element on a semiconductor body comprising silicon and utilizing a silicon integrated circuit technology.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A process for producing olefin by catalytic cracking of hydrocarbon material characterized in employing zeolite of penta-sil type comprising rare earth elements and at least one of manganese or zirconium as a catalyst.
2. The process for producing olefin according to claim 1, wherein the contents of said rare earth elements in said catalyst falls within the range of from 0.4 to 20 expressed as atomic ratio of aluminum in zeolite.
3. The process for producing olefin according to claim 1, wherein the total contents of manganese and zirconium in said catalyst falls within the range of from 0.1 to 20 expressed as mole ratio of aluminum in zeolite.
4. The process for producing olefin according to claim 1, wherein said catalyst further comprises phosphorous in an amount of from 0.1 to 5% by mole.
5. The process for producing olefin according to claim 1, wherein the mole ratio of SiO2Al2O3 among zeolite in said catalyst is from 25 to 800.
6. The process for producing olefin according to claim 1, wherein a catalytic reaction is carried out under the presence of steam.