1. A semiconductor structure comprising:
an electronic device formed on a first side of the semiconductor structure; and
a thermoelectric cooling device formed on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction.
2. The semiconductor structure of claim 1, wherein the thermoelectric cooling device includes thermoelectric material.
3. The semiconductor structure of claim 2, wherein the thermoelectric cooling device includes two or more Peltier junctions that are connected by TiNAl, aluminum, andor TiCu.
4. The semiconductor structure of claim 1, wherein the thermoelectric cooling device is configured to be energized using a through silicon via that extends from the thermoelectric cooling device to contacts on the first side of the semiconductor structure.
5. The semiconductor structure of claim 1, wherein the second side of the semiconductor structure includes polyimide or insulator material and the thermoelectric cooling device is formed therein.
6. The semiconductor structure of claim 4, further comprising a bond pad andor a metal contact formed on the second side of the semiconductor structure in proximity to the through silicon via, and wherein the thermoelectric cooling device is formed on the bond pad andor metal contact.
7. The semiconductor structure of claim 1, further comprising a heat sink affixed to the second side of the semiconductor structure proximate to the thermoelectric device.
8. The semiconductor structure of claim 7, wherein the heat sink is affixed to the second side of the semiconductor structure using a thermal interface material.
9. The semiconductor structure of claim 1, further comprising another semiconductor structure affixed to the second side of the semiconductor structure.
10. The semiconductor structure of claim 7, wherein the heat sink includes a low-k dielectric material andor conducting material.
11. The semiconductor structure of claim 1, wherein the electronic device is a field effect transistor.
12. The semiconductor structure of claim 1, wherein the thermoelectric cooling device includes n-type and p-type semiconductor material.
13. A method comprising:
forming an electronic device on a first side of a semiconductor structure; and
forming a thermoelectric cooling device on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction.
14. The method of claim 13, wherein the thermoelectric cooling device includes thermoelectric material.
15. The method of claim 14, wherein the thermoelectric cooling device includes two or more Peltier junctions that are connected by TiNAl, aluminum, andor TiCu.
16. The method of claim 13, wherein the thermoelectric cooling device is configured to be energized using a through silicon via that extends from the thermoelectric cooling device to contacts on the first side of the semiconductor structure.
17. The method of claim 13, further comprising:
forming polyimide or insulator material on the second side of the semiconductor structure; and
forming the thermoelectric device in the polyimide or insulator material.
18. The method of claim 13, further comprising:
forming a bond pad or a metal contact on the second side of the semiconductor structure in proximity to the through silicon via; and
forming the thermoelectric device on the bond pad or the metal contact.
19. The method of claim 13, further comprising affixing a heat sink proximate to the thermoelectric device that includes a low-k dielectric material andor conducting material.
20. The method of claim 13, wherein the electronic device is a field effect transistor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A capacitor-averaging pipeline analog-to-digital converter comprising a plurality of stages, each of the plurality of stages comprising a first switched capacitor circuit and a second switched capacitor circuit parallel with the first switched capacitor circuit, wherein each of the plurality of stages is able to operate in a two-phase clock scheme and for every two phases there is one residual signal generated.
2. The converter as claimed in claim 1, wherein the second switched capacitor circuit is the same as the first switched capacitor circuit.
3. The converter as claimed in claim 1, wherein the second switched capacitor circuit is exactly the same as the first switched capacitor circuit.
4. The converter as claimed in claim 1, wherein the first switched capacitor circuit of one of the plurality of stages is the same as the first switched capacitor circuit of a second of the plurality of stages.
5. The converter as claimed in claim 4,wherein the second switched capacitor circuit of the one stage is the same as the second switched capacitor circuit of the second stage.
6. The converter as claimed in claim 1, wherein the first switched capacitor circuit of one of the plurality of stages is different from the first switched capacitor circuit of a second of the plurality of stages.
7. The converter as claimed in claim 6, wherein the second switched capacitor circuit of the one stage is different to the second switched capacitor circuit of the second stage.
8. A capacitor-averaging pipeline analog-to-digital converter comprising a plurality of stages, each of the plurality of stages comprising a first switched capacitor circuit and a second switched capacitor circuit parallel with the first switched capacitor circuit wherein the second switched capacitor circuit is for simultaneous residual signal amplification and averaging when the first switched capacitor circuit is sampling an input signal, and the first switched capacitor circuit is for simultaneous residual signal amplification and averaging when the second switched capacitor circuit is sampling an input signal.
9. The converter as claimed in claim 8 further comprising an operational amplifier for each of the plurality of stages, wherein for each of the plurality of stages outputs of the first switched capacitor circuit and the second switched capacitor circuit are configured to be input to the operational amplifier, the operational amplifier being configured for continuous operational during conversion.
10. A method of converting an analog signal to a digital signal, the method comprising:
during a first phase of a clock cycle: sampling an input signal at a first switched capacitor circuit of a first stage of a plurality of stages of a capacitor-averaging pipeline analog-to-digital converter, and performing residual amplification and averaging of an earlier input signal sampled from a previous phase of the clock cycle at a second switched capacitor circuit of the first stage of the plurality of stages of the capacitor-averaging pipeline analog-to-digital converter;
during a second phase of the clock cycle: sampling the input signal at the second switched capacitor circuit, and performing residual amplification and averaging of the input signal sampled from the previous phase of the clock cycle at the first switched capacitor circuit.
11. The method as claimed in claim 10, wherein an averaged residual signal from the first stage is input to a second stage of the plurality of stages.
12. The method as claimed in claim 11, wherein
during the first phase of the clock cycle: the averaged residual signal generated from the first stage is sampled into a first switched capacitor circuit of the second stage, and an earlier averaged residual signal sampled from a previous phase of the clock cycle is amplified and averaged at a second switched capacitor circuit of the second stage;
during the second phase of the clock cycle: the averaged residual signal generated from the first stage is sampled into the second switched capacitor circuit of the second stage, and the averaged residual signal sampled from the previous phase of the clock cycle is amplified and averaged at the first switched capacitor circuit of the second stage.
13. The method as claimed in claim 10, wherein each of the plurality of stages of the capacitor-averaging pipeline analog-to-digital converter comprises an operational amplifier, for each of the plurality of stages outputs of the first switched capacitor circuit and the second switched capacitor circuit are input to the operational amplifier, the operational amplifier being in continuous operational during conversion.
14. The method as claimed in claim 10, wherein each of the plurality of stages operates in a two-phase clock scheme.