1. An exercise apparatus comprising:
a frame having a base portion and having first and second right support elements and first and second left support elements;
a crank system comprising first and second crank coupling locations, the crank system being supported by the frame;
a right foot support member;
a left foot support member;
a right guide element coupled to the right foot support member;
a left guide element coupled to the left foot support member;
a first flexible support system comprising a first flexible element, the first flexible element coupled to the first and second right support elements and the right guide element and coupled to the first crank coupling location; and
a second flexible support system comprising a second flexible element, the second flexible element coupled to the first and second left support elements and the left guide element and coupled to the second crank coupling location, wherein alternating motion of the right and left foot support members causes the first and second crank coupling locations to rotate.
2. The exercise apparatus of claim 1 wherein said right guide element is located below and horizontally intermediate the first and second right support elements at some time during operation of the exercise apparatus, and wherein said left guide element is located below and horizontally intermediate the first and second left support elements at some time during operation of the exercise apparatus.
3. The exercise apparatus of claim 1 wherein the right and left foot support members each trace a substantially closed path, the shape of the path selected from the list consisting of;
an ellipse;
an oval;
an approximate ellipse; and
a saddle shape.
4. The system of claim 1 wherein the right and left foot support members each trace a substantially closed path, and the curvature of the shape of the path continuously changes during the left and right striding motions.
5. The exercise apparatus of claim 1 further comprising:
a right arcuate motion member coupled to the right foot support member and pivotally coupled to the frame and providing relative rotation with regard to the right foot support member; and
a left arcuate motion member coupled to the left foot support member and pivotally coupled to the frame and providing relative rotation with regard to the left foot support member.
6. The exercise apparatus of claim 5, wherein the left and right arcuate motion members and the left and right foot support members form an assembly wherein the respective left and right sides are cross-coupled by a cross coupling system to provide alternating motion.
7. The exercise apparatus of claim 6, wherein said cross coupling system is coupled to a brake.
8. The exercise apparatus of claim 6 wherein the cross-coupling is provided by mechanisms selected from the list comprising:
a belt loop; and
a rocker mechanism coupled to the left and right arcuate motion members.
9. The exercise apparatus of claim 1 further comprising one or more of the following:
a brake device coupled to the crank system; and
an inertia device coupled to the crank system.
10. The exercise apparatus of claim 1 wherein the first and second flexible elements are selected from the list consisting of:
a belt;
a cog;
a chain; and
a cable.
11. The exercise apparatus of claim 1, wherein the right and left foot support members each trace a substantially closed path, and a change in force applied to the left and right foot support members changes the shape of the paths.
12. The exercise apparatus of claim 1 further comprising:
an intermediate linkage system coupling the first and second flexible elements to the first and second crank coupling locations.
13. The exercise apparatus of claim 1 wherein the second left and right support elements are included on intermediate linkage assemblies coupling the first and second flexible elements to the first and second crank coupling locations.
14. The exercise apparatus of claim 13 wherein the motion of the right foot support member continuously varies a vertical position of the second right support element, thereby rotating the crank coupling locations, and wherein the motion of the left foot support member continuously varies a vertical position of the second left support element, thereby rotating the crank coupling locations.
15. The exercise apparatus of claim 13 wherein the motion of the right foot support member continuously changes a distance between the first and second right support elements, thereby rotating the crank coupling locations and affecting a shape of the path traced by the right foot support member, and wherein the striding motion applied to the left foot support member continuously changes a distance between the first and second left support elements, thereby rotating the crank coupling locations and affecting the shape of the path traced by the left foot support member.
16. The exercise apparatus of claim 1, wherein the right guide element comprises:
a plurality of pulley components, each contacting the first flexible element in a different place; and
wherein the left guide element comprises:
a plurality of pulley components, each contacting the second flexible element in a different place.
17. The exercise apparatus of claim 1 further comprising:
a brake device coupled to the crank system at a rearward portion of the frame.
18. The exercise apparatus of claim 1 wherein said first and second crank coupling locations are located on crank arms.
19. The exercise apparatus of claim 1 wherein said crank system comprises:
a counterweight.
20. The exercise apparatus of claim 1, wherein at least one of said guide elements is coupled to a brake.
21. A method for operating a exercise system, the exercise system including a frame, a crank system supported by the frame and including a crank shaft, first and second flexible elements, each in communication with both the frame and the crank system, a right foot support member comprising a right guide element that is coupled to the first flexible element, a left foot support member comprising a left guide element that is coupled to the second flexible element, first and second right support elements supporting the first flexible element, and first and second left support elements supporting the second flexible element, the method comprising:
applying force to the right foot support member, thereby varying a geometric relationship among the first right support element, the right guide element, and the second right support element; and
applying force to the left foot support member, thereby varying a geometric relationship among the first left support element, the left guide element, and the second left support element.
22. The method of claim 21 further comprising:
rotating the crank shaft; and
tracing substantially closed paths with the right and left foot support members during striding motion.
23. The method of claim 21 further comprising:
varying a horizontal and vertical position of the second right support members during striding motion; and
varying a horizontal and vertical position of the second left support members during striding motion.
24. The method of claim 21 wherein the stationary exercise system further comprises:
right and left arcuate motion members respectively coupled to the right and left foot support members; and
alternately moving the right and left motion members, thereby contributing to a striding motion.
25. The method of claim 21 wherein:
the applying force to the right foot support member includes varying a length of the first flexible support element between the first right support element and the right guide element and a length of the first flexible support element between the second right support element and the right guide element; and
the applying force to the left foot support member includes varying a length of the second flexible support element between the first left support element and the left guide element and a length of the second flexible support element between the second left support element and the left guide element.
26. An exercise apparatus comprising:
a frame having a base portion and having first and second right support elements and first and second left support elements, the first and second right support elements separated by a horizontal length L, the first and second left support elements separated by a horizontal length L\u2032;
a crank system supported by the frame and having first and second crank coupling locations, the crank system supported by the frame;
a right foot support member having a right guide element coupled to the right foot support and located horizontally intermediate the first and second right support elements at some time during operation of the exercise apparatus;
a left foot support member having a left guide element coupled to the left foot support and located horizontally intermediate the first and second left support elements at some time during operation of the exercise apparatus;
a first flexible support system comprising a first flexible element, the first flexible element coupled to the first and second right support elements, the right guide element, and the first crank coupling location, the first flexible element having a length A between the right guide element and the first right support element and a length B between the right guide element and the second right support element;
a second flexible support system comprising a second flexible element, the second flexible element coupled to the first and second left support elements, the left guide element, and the second crank coupling location, the second flexible element having a length A\u2032 between the left guide element and the first left support element and a length B\u2032 between the left guide element and the second left support element; and
wherein striding motion applied to the right foot support member continuously varies a geometric relationship between the right foot support member and the first and second right support elements, thereby rotating the crank coupling locations, and wherein striding motion applied to the left foot support member continuously varies a geometric relationship between the left foot support member and the first and second left support elements, thereby rotating the crank coupling locations.
27. The exercise apparatus of claim 26 wherein the striding motion applied to the right foot support member continuously varies A and B, thereby determining a shape of a path traced by the right foot support member, and wherein the striding motion applied to the left foot support member continuously varies A\u2032 and B\u2032, thereby determining the shape of the path traced by the left foot support member.
28. The exercise apparatus of claim 26 wherein the right and left foot support members each trace a substantially closed path, the shape of the path selected from the list consisting of:
an ellipse;
an oval;
an approximate ellipse; and
a saddle shape.
29. The system of claim 26 wherein the right and left foot support members each trace a substantially closed path, and a change in force applied to the left and right foot support members changes the shape of the paths.
30. The exercise apparatus of claim 26 further comprising:
a right arcuate motion member pivotally coupled to the right foot support member and pivotally coupled to the frame; and
a left arcuate motion member pivotally coupled to the left foot support member and pivotally coupled to the frame.
31. The exercise apparatus of claim 30, wherein the left and right arcuate motion members and the left and right foot support members form an assembly wherein the respective left and right sides are cross-coupled by a cross coupling system to provide alternating motion.
32. The exercise apparatus of claim 31 wherein said cross coupling system is coupled to a brake.
33. The exercise apparatus of claim 31 wherein the cross-coupling is provided by mechanisms selected from the list comprising:
a belt loop; and
a rocker mechanism coupled to the left and right arcuate motion members.
34. The exercise apparatus of claim 26 further comprising one or more of the following:
a brake device coupled to the crank system; and
an inertia device coupled to the crank system.
35. The exercise apparatus of claim 26 wherein the first and second flexible elements are selected from the list consisting of;
a belt;
a cog;
a chain; and
a cable.
36. The exercise apparatus of claim 26 further comprising:
an intermediate linkage system coupling the first and second flexible elements to the crank coupling locations.
37. The exercise apparatus of claim 26 wherein the second left and right support elements are included on intermediate linkage assemblies coupling the first and second flexible elements to the crank coupling locations.
38. The exercise apparatus of claim 37 wherein the striding motions applied to the right foot support member continuously varies L and a vertical position of the second right support element, thereby rotating the crank coupling locations and determining a shape of a substantially closed path traced by the right foot support member, and wherein the striding motion applied to the left foot support member continuously varies L\u2032 and a vertical position of the second left support element, thereby rotating the crank coupling locations and determining a shape of a substantially closed path traced by the left foot support member.
39. The exercise apparatus of claim 37 wherein the striding motion applied to the right foot support member continuously varies a distance between the first and second right support elements, thereby rotating the crank coupling locations and affecting a shape of a substantially closed path traced by the right foot support member, and wherein the striding motion applied to the left foot support member continuously varies a distance between the first and second left support elements, thereby rotating the pivot points and affecting a shape of a substantially closed path traced by the left foot support member.
40. The exercise apparatus of claim 26, wherein the right guide element comprises:
a plurality of pulley components, each contacting the first flexible element in a different place; and
wherein the left guide element comprises:
another plurality of pulley components, each contacting the second flexible element in a different place.
41. The exercise apparatus of claim 26 further comprising:
a brake device coupled to the crank system at a rearward portion of the frame.
42. The exercise apparatus of claim 26, wherein at least one of said guide elements is coupled to a brake.
43. The exercise apparatus of claim 26 wherein the crank system comprises:
a counterweight.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for clearing address translation buffer entries in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the method comprising the steps of:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
2. The method according to claim 1 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
3. The method according to claim 1 wherein the first translation table origin address comprises any one an Address Space Control Element (ASCE) address, a region table origin address, a page table origin address or a segment table origin address
4. The method according to claim 1 wherein the first translation table origin address comprises a first translation table entry of a range of two or more translation table entries.
5. The method according to claim 3 comprising the further step of invalidating the range of two or more translation table entries.
6. The method according to claim 1 wherein the computer system comprises architected general purpose registers, wherein the address translation tables consist of page tables and any one of:
one or more segment tables,
one or more segment tables and one or more first region tables,
one or more segment tables and one or more first region tables and one or more second region tables or
one or more segment tables and one or more first region tables and one or more second region tables and one or more third region tables;
wherein further, a segment table entry comprises a page table origin;
the method comprising the further steps of:
retrieving first information from a location specified by the instruction, the first information comprising an indication of the operation of the instruction; and
based on the first information, determining that the instruction is configured to initiate the execution of the clear operation.
7. The method according to claim 6, wherein the first information indicates the instruction is configured to initiate execution of a clear operation when bit 52 of the first information is 1.
8. The method according to claim 1 comprising the further steps of:
the computer system fetching the instruction from a main storage, the instruction comprising:
a second field for locating second information, the second information comprising the clearing information for the clear operation;
determining from the opcode of the instruction fetched that the instruction fetched is the instruction having the clear operation;
i) determining if a predetermined address translation buffer entry portion of an address translation buffer entry of an address translation buffer comprises the second information; and
j) clearing the address translation buffer entry determined to comprise the second information; and
k) repeating steps i)-j) for a plurality of address translation buffer entries.
9. The method according to claim 8 wherein the second field locates the second information in a second architected general purpose register.
10. The method according to claim 8 wherein when the second field is 0, any one of:
any address translation buffer entry is cleared, or
the second information comprises the first translation table origin address.
11. The method according to claim 8, comprising the further steps of:
when the second field is 0, the second information is formed from the ASCE; and
when the second field is greater than 0, retrieving second information from an architected general register.
12. The method according to claim 1 comprising the further steps of:
interpreting the instruction to identify a predetermined software routine for emulating the operation of the instruction, the predetermined software routine comprising a plurality of instructions; and
executing the predetermined software routine.
13. The method according to claim 1 wherein the address translation buffer is a translation lookaside buffer (TLB).
14. The method according to claim 1 wherein the address translation buffer is any one of:
an address translation buffer associated with a first central processing unit of the computer system, the first central processing unit executing the instruction,
an address translation buffer associated with a second central processing unit of the computer system, or
all address translation buffers associated with the computer system.
15. The method according to claim 1, wherein the computer system further comprises page tables, the page tables having real main storage addresses, wherein real main storage addresses comprise any one of an absolute address, a real address or a physical address.
16. A computer program product for clearing address translation buffer entries in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the computer program product comprising:
a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
17. The method according to claim 16 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
18. The computer program product according to claim 16 wherein the first translation table origin address comprises any one of an Address Space Control Element (ASCE) address, a region table origin address, a page table origin address or a segment table origin address
19. The computer program product according to claim 16 wherein the first translation table origin address comprises a first translation table entry of a range of two or more translation table entries.
20. The computer program product according to claim 19 comprising the further step of invalidating the range of two or more translation table entries.
21. The computer program product according to claim 16 wherein the computer system comprises architected general purpose registers, wherein the address translation tables consist of page tables and any one of:
one or more segment tables,
one or more segment tables and one or more first region tables,
one or more segment tables and one or more first region tables and one or more second region tables or
one or more segment tables and one or more first region tables and one or more second region tables and one or more third region tables;
wherein further, a segment table entry comprises a page table origin;
the computer program product comprising the further steps of:
retrieving first information from a location specified by the instruction, the first information comprising an indication of the operation of the instruction; and
based on the first information, determining that the instruction is configured to initiate the execution of the clear operation.
22. The computer r program product according to claim 21, wherein the first information indicates the instruction is configured to initiate execution of a clear operation when bit 52 of the first information is 1.
23. The computer program product according to claim 17 comprising the further steps of:
the computer system fetching the instruction from a main storage, the instruction comprising:
a second field for locating second information, the second information comprising the clearing information for the clear operation;
determining from the opcode of the instruction fetched that the instruction fetched is the instruction having the clear operation;
i) determining if a predetermined address translation buffer entry portion of an address translation buffer entry of an address translation buffer comprises the second information; and
j) clearing the address translation buffer entry determined to comprise the second information; and
k) repeating steps i)-j) for a plurality of address translation buffer entries.
24. The computer program product according to claim 22 wherein the second field locates the second information in a second architected general purpose register.
25. The computer program product according to claim 22 wherein when the second field is 0, any one of:
any address translation buffer entry is cleared, or
the second information comprises the first translation table origin address.
26. The computer program product according to claim 23, comprising the further steps of:
when the second field is 0, the second information is formed from the ASCE; and
when the second field is greater than 0, retrieving second information from an architected general register.
27. The computer program product according to claim 17 comprising the further steps of:
interpreting the instruction to identify a predetermined software routine for emulating the operation of the instruction, the predetermined software routine comprising a plurality of instructions; and
executing the predetermined software routine.
28. The computer program product according to claim 17 wherein the address translation buffer is a translation lookaside buffer (TLB).
29. The computer program product according to claim 17 wherein the address translation buffer is any one of:
an address translation buffer associated with a first central processing unit of the computer system, the first central processing unit executing the instruction,
an address translation buffer associated with a second central processing unit of the computer system, or
all address translation buffers associated with the computer system.
30. The computer program product according to claim 17, wherein the computer system further comprises page tables, the page tables having real main storage addresses, wherein real main storage addresses comprise any one of an absolute address, a real address or a physical address.
31. A system for clearing address translation buffers in a computer system, the system comprising:
a main storage;
one or more central processing units in communications with the main storage, the central processing units comprising:
architected general purpose registers;
address translation buffers, an address translation buffer having address translation buffer entries holding address translation information;
a plurality of address translation tables for translating virtual main storage addresses of a central processing unit of the one or more processing units to main storage addresses of the computer system;
one or more instruction execution units, the instruction execution units in communication with the architected general purpose registers, the instruction execution units executing machine instructions fetched from the main storage;
wherein the computer system includes instructions to execute a method comprising:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
32. The method according to claim 31 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
33. The system according to claim 31 wherein the first translation table origin address comprises any one of an Address Space Control Element (ASCE) address, a region table origin address, a page table origin address or a segment table origin address
34. The system according to claim 31 wherein the first translation table origin address comprises a first translation table entry of a range of two or more translation table entries.
35. The system according to claim 34 comprising the further step of invalidating the range of two or more translation table entries.
36. The system according to claim 31 wherein the computer system comprises architected general purpose registers, wherein the address translation tables consist of page tables and any one of:
one or more segment tables,
one or more segment tables and one or more first region tables,
one or more segment tables and one or more first region tables and one or more second region tables or
one or more segment tables and one or more first region tables and one or more second region tables and one or more third region tables;
wherein further, a segment table entry comprises a page table origin;
the system comprising the further steps of:
retrieving first information from a location specified by the instruction, the first information comprising an indication of the operation of the instruction; and
based on the first information, determining that the instruction is configured to initiate the execution of the clear operation.
37. The system according to claim 36, wherein the first information indicates the instruction is configured to initiate execution of a clear operation when bit 52 of the first information is 1.
38. The system according to claim 31 comprising the further steps of:
the computer system fetching the instruction from a main storage, the instruction comprising:
a second field for locating second information, the second information comprising the clearing information for the clear operation;
determining from the opcode of the instruction fetched that the instruction fetched is the instruction having the clear operation;
i) determining if a predetermined address translation buffer entry portion of an address translation buffer entry of an address translation buffer comprises the second information; and
j) clearing the address translation buffer entry determined to comprise the second information; and
k) repeating steps i)-j) for a plurality of address translation buffer entries.
39. The system according to claim 38 wherein the second field locates the second information in a second architected general purpose register.
40. The system according to claim 38 wherein when the second field is 0, any one of:
any address translation buffer entry is cleared, or
the second information comprises the first translation table origin address.
41. The system according to claim 38, comprising the further steps of:
when the second field is 0, the second information is formed from the ASCE; and
when the second field is greater than 0, retrieving second information from an architected general register.
42. The system according to claim 31 comprising the further steps of:
interpreting the instruction to identify a predetermined software routine for emulating the operation of the instruction, the predetermined software routine comprising a plurality of instructions; and
executing the predetermined software routine.
43. The system according to claim 31 wherein the address translation buffer is a translation lookaside buffer (TLB).
44. The system according to claim 31 wherein the address translation buffer is any one of:
an address translation buffer associated with a first central processing unit of the computer system, the first central processing unit executing the instruction,
an address translation buffer associated with a second central processing unit of the computer system, or
all address translation buffers associated with the computer system.
45. The system according to claim 31, wherein the computer system further comprises page tables, the page tables having real main storage addresses, wherein real main storage addresses comprise any one of an absolute address, a real address or a physical address.
46. A method for clearing address translation buffer entries in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the method comprising the steps of:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, wherein the first translation table origin address comprises any one of an Address Space Control Element (ASCE) address, a region table origin address, a page table origin address or a segment table origin address, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
47. The method according to claim 46 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
48. A method for clearing address translation buffer entries in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the method comprising the steps of:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, wherein the first translation table origin address comprises a first translation table entry of a range of two or more translation table entries, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
49. The method according to claim 48 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
50. The method according to claim 49 comprising the further step of invalidating the range of two or more translation table entries.
51. A system for clearing address translation buffers in a computer system, the system comprising:
a main storage;
one or more central processing units in communications with the main storage, the central processing units comprising:
architected general purpose registers;
address translation buffers, an address translation buffer having address translation buffer entries holding address translation information;
a plurality of address translation tables for translating virtual main storage addresses of a central processing unit of the one or more processing units to main storage addresses of the computer system;
one or more instruction execution units, the instruction execution units in communication with the architected general purpose registers, the instruction execution units executing machine instructions fetched from the main storage;
wherein the computer system includes instructions to execute a method comprising:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, wherein the first translation table origin address comprises any one of an Address Space Control Element (ASCE) address, a region table origin address, a page table origin address or a segment table origin address, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
52. The system according to claim 51 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
53. A system for clearing address translation buffers in a computer system, the system comprising:
a main storage;
one or more central processing units in communications with the main storage, the central processing units comprising:
architected general purpose registers;
address translation buffers, an address translation buffer having address translation buffer entries holding address translation information;
a plurality of address translation tables for translating virtual main storage addresses of a central processing unit of the one or more processing units to main storage addresses of the computer system;
one or more instruction execution units, the instruction execution units in communication with the architected general purpose registers, the instruction execution units executing machine instructions fetched from the main storage;
wherein the computer system includes instructions to execute a method comprising:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, wherein the first translation table origin address comprises a first translation table entry of a range of two or more translation table entries, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
54. The system according to claim 53 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
55. The system according to claim 53 comprising the further step of invalidating the range of two or more translation table entries.
56. A computer program product for clearing address translation buffer entries in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the computer program product comprising:
a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, wherein the first translation table origin address comprises any one of an Address Space Control Element (ASCE) address, a region table origin address, a page table address or a segment table origin address, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
57. The computer program product according to claim 56 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
58. A computer program product for clearing address translation buffer entries in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the computer program product comprising:
a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining from an opcode of a machine executable instruction to be executed that the instruction is configured to initiate execution of a clear operation;
executing the instruction, the executing step comprising the steps of:
based on a first translation table origin address of a first translation table, wherein the first translation table origin address comprises a first translation table entry of a range of two or more translation table entries, selectively clearing one or more first entries of the address translation buffer from the address translation buffer, the one or more first entries associated with the first translation table origin address.
59. The computer program product according to claim 58 wherein the clearing step does not clear one or more second entries of the address translation buffer in the address translation buffer, the one or more second entries not associated with the first translation table origin address.
60. The computer program product according to claim 59 comprising the further step of invalidating the range of two or more translation table entries.
61. A method for clearing address translation buffer entries of a translation lookaside buffer (TLB) address translation buffer in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the method comprising the steps of:
the computer system fetching a Dynamic Address Translation Table Entry (IDTE) instruction from a main storage, the instruction comprising an opcode and a second field for determining second information, the second information comprising an address space control element (ASCE) address or an origin address of an address translation table consisting of:
a first region table having entries comprising addresses of a second region table origins,
a second region table having entries comprising addresses of third region table origins,
a third region table having entries comprising addresses of segment table origin,
a segment table having entries comprising addresses of page table origins wherein a page table comprise memory addresses, or
a page table having entries comprising addresses of main storage;
determining from the opcode that the instruction is configured to initiate execution of a clear operation; and
executing the instruction, the executing step comprising the steps of:
i) determining if an address translation buffer entry of an address translation buffer is related to the second information; and
j) clearing the address translation buffer entry determined to be related to the second information; and
k) repeating steps i)-j) for a plurality of address translation buffer entries.
62. The method according to claim 61, wherein the computer system comprises a plurality of TLBs comprising the further step of performing steps i)-k) for the plurality of TLBs of the computer system.
63. The method according to claim 61, comprising the farther steps of:
interpreting the instruction to identify a predetermined software routine for emulating steps of the method, the predetermined software routine comprising a plurality of instructions; and
executing the predetermined software routine.
64. A computer program product for clearing address translation buffers address translation buffer entries of a translation lookaside buffer (TLB) address translation buffer in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the computer program product comprising:
a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
the computer system fetching a Dynamic Address Translation Table Entry (IDTE) instruction from a main storage, the instruction comprising an opcode and a second field for determining second information, the second information comprising an address space control element (ASCE) address or an origin address of an address translation table consisting of:
a first region table having entries comprising addresses of a second region table origins,
a second region table having entries comprising addresses of third region table origins,
a third region table having entries comprising addresses of segment table origins,
a segment table having entries comprising addresses of page table origins wherein a page table comprise memory addresses, or
a page table having entries comprising addresses of main storage;
determining from the opcode that the instruction is configured to initiate execution of a clear operation; and
executing the instruction, the executing step comprising the steps of:
i) determining if an address translation buffer entry of an address translation buffer is related to the second information; and
j) clearing the address translation buffer entry determined to be related to the second information; and
k) repeating steps i)-j) for a plurality of address translation buffer entries.
65. The computer program product according to claim 64, wherein the computer system comprises a plurality of TLBs comprising the further step of performing steps i)-k) for the plurality of TLBs of the computer system.
66. The computer program product according to claim 64, comprising the further steps of:
interpreting the instruction to identify a predetermined software routine for emulating steps of the method, the predetermined software routine comprising a plurality of instructions; and
executing the predetermined software routine.
67. A system for clearing address translation buffers in a computer system, the system comprising:
a main storage;
one or more central processing units in communications with the main storage, the central processing units comprising:
architected general purpose registers;
one or more translation lookaside buffer (TLB) address translation buffers, an address translation buffer having address translation buffer entries holding address translation information;
a plurality of address translation tables for translating virtual main storage addresses of a central processing unit of the one or more processing units to main storage addresses of the computer system;
one or more instruction execution units, the instruction execution units in communication with the architected general purpose registers, the instruction execution units executing machine instructions fetched from the main storage;
wherein the computer system includes instructions to execute a method comprising:
the computer system fetching a Dynamic Address Translation Table Entry (IDTE) instruction from a main storage, the instruction comprising an opcode and a second field for determining second information, the second information comprising an address space control element (ASCE) address or an origin address of an address translation table consisting of:
a first region table having entries comprising addresses of a second region table origins,
a second region table having entries comprising addresses of third region table origins,
a third region table having entries comprising addresses of segment table origins,
a segment table having entries comprising addresses of page table origins wherein a page table comprise memory addresses, or
a page table having entries comprising addresses of main storage;
determining from the opcode that the instruction is configured to initiate execution of a clear operation; and
executing the instruction, the executing step comprising the steps of:
i) determining if an address translation buffer entry of an address translation buffer is related to the second information; and
j) clearing the address translation buffer entry determined to be related to the second information; and
k) repeating steps i)-j) for a plurality of address translation buffer entries.
68. The system according to claim 67, wherein the computer system comprises a plurality of TLBs comprising the further step of performing steps i)-k) for the plurality of TLBs of the computer system.
69. The system according to claim 67, comprising the further steps of:
interpreting the instruction to identify a predetermined software routine for emulating steps of the system, the predetermined software routine comprising a plurality of instructions; and
executing the predetermined software routine.