1. A method for measuring a write current of a semiconductor memory device, comprising the steps of:
selecting a memory cell whose write current is to be measured among memory cells,
programming initial data into the memory cells which are to be programmed at substantially the same time;
determining whether the memory cells are programmed into a same state or not;
inputting test data when the memory cells are programmed into the same state, wherein a selected bit of the test data is configured to have an opposite logical level to a corresponding bit of the initial data and the selected bit is to be programmed into the selected memory cell;
setting write current paths of the memory cells by comparing the initial data and the test data; and
measuring the write current of the selected memory cell when the test data are programmed into the memory cells.
2. The method according to claim 1, wherein the step of setting the write current paths comprises the step of forming a write current path of the selected memory cell.
3. The method according to claim 1, wherein the initial data programmed into the respective memory cells are at a logic low level,
the selected bit of the test data programmed into the selected memory cell is at a logic high level, and
other bits of the test data programmed into other memory cells except the selected memory cell of the memory cells are at a logic low level.
4. The method according to claim 1, wherein the initial data programmed into the respective memory cells are at a logic high level,
the selected bit of the test data programmed into the selected memory cell is at a logic low level, and
other bits of the test data programmed into other memory cells except the selected memory cell of the memory cells are at a logic high level.
5. A semiconductor memory device comprising:
a plurality of memory cells configured to be programmed at substantially the same time, wherein the memory cells comprise a selected memory cell whose write current is to be measured;
a plurality of write drivers allocated to the respective memory cells and configured to provide a write current set according to the state of input data to the respective memory cells; and
a plurality of write current path control units allocated to the respective memory cells and configured to compare initial data programmed into the respective memory cells to test data to be programmed into the respective memory cells and set a write current path between the memory cells and the corresponding write drivers according to the comparison result, during a test operation,
wherein bits of the initial data are configured to have the same logical levels, wherein a selected bit of the test data is configured to have an opposite logical level to a corresponding bit of the initial data and the selected bit is to be programmed into the selected memory cell.
6. The semiconductor memory device according to claim 5, wherein when the initial data and the test data have opposite values, the write current path control units form write current paths between the corresponding memory cells and the corresponding write drivers.
7. The semiconductor memory device according to claim 6, wherein the write current path control units are formed inside the corresponding write drivers, respectively.
8. The semiconductor memory device according to claim 7, wherein the write drivers comprise current sources for applying a write current to the respective memory cells, and
the write current path control units enable the current sources of the corresponding write drivers.
9. The semiconductor memory device according to claim 7, further comprising bit lines connected between the write drivers and the memory cells, respectively.
10. The semiconductor memory device according to claim 6, wherein the write current path control units are formed outside the corresponding write drivers.
11. The semiconductor memory device according to claim 10, further comprising switches connected between the memory cells and the write drivers, and
the write current path control units form the write current paths according to control of the corresponding switches.
12. The semiconductor memory device according to claim 11, further comprising bit lines connected between the switches and the write drivers.
13. The semiconductor memory device according to claim 5, wherein each of the write current path control units comprises:
an initial data storing block configured to store the initial data; and
a compare block configured to compare the initial data stored in the initial data storing block to the test data, and output a control signal for setting the write current path according to the comparison result.
14. The semiconductor memory device according to claim 5, wherein the memory cells are connected to different inputoutput pins.
15. The semiconductor memory device according to claim 5, wherein the memory cells comprise a memory element and a selecting element, the memory element having a variable resistance value depending on an applied current to the memory element.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A magnetic field force generator having a predefined force profile comprising:
a first magnet structure comprising a first plurality of magnets arranged according to a first pattern; and
a complementary magnet structure comprising a complementary plurality of magnets complementary to said first magnet structure;
said first pattern based on a variable code having an autocorrelation function with a single maximum peak per code modulo;
said first magnet structure and said complementary magnet structure having an operational range of relative position; wherein magnetic force between said first magnet structure and said complementary magnet structure as a function of position within said operational range corresponds to said autocorrelation function.
2. The magnetic field force generator as recited in claim 1, wherein the variable code is a cyclic code.
3. The magnetic field force generator as recited in claim 1, wherein the variable code is a non-cyclic code.
4. The magnetic field force generator as recited in claim 1, wherein the first plurality is N magnets, the single maximum peak is N, and a maximum autocorrelation magnitude offset from said single maximum peak is |N2| or less.
5. The magnetic field force generator as recited in claim 1, wherein the first plurality is N magnets, the single maximum peak is N, and a maximum autocorrelation magnitude offset from said single maximum peak is |2|.
6. The magnetic field force generator as recited in claim 1, wherein the first plurality is N magnets, the single maximum peak is N, and a maximum autocorrelation magnitude offset from said single maximum peak is |1|.
7. The magnetic field force generator as recited in claim 1, wherein the first plurality is N magnets, the single maximum peak is N, and a correlation offset from said single maximum peak is \u22121.
8. The magnetic field force generator as recited in claim 1, wherein said first plurality of magnets arranged according to said first pattern comprises a magnet pattern of nine component magnets at relative coordinates of
+1(0,0), \u22121(0,1), +1(0,2), \u22121(1,0.5), +1(1,1.5), \u22121(1,2.5), +1(2,0), \u22121(2,1), +1(2,2),
or said magnet pattern reflected about the x axis, or said magnet pattern reflected about the y axis, or said magnet pattern with the x and y axes transposed, where within the notation s(x,y), \u201cs\u201d indicates the respective component magnet strength and polarity and \u201c(x,y)\u201d indicates x and y coordinates of a center of the respective component magnet relative to a reference position (0,0).
9. The magnetic field force generator as recited in claim 1, wherein said first plurality of magnets arranged according to said first pattern comprises a magnet pattern of nineteen component magnets at relative coordinates:
\u22121(3,7), \u22121(4,5), \u22121(4,7), +1(5,3), +1(5,7), \u22121(5,11), +1(6,5), \u22121(6,9), +1(7,3), \u22121(7,7), +1(7,11), \u22121(8,5), \u22121(8,9), +1(9,3), \u22121(9,7), +1(9,11), +1(10,5), \u22121(10,9) +1(11,7), or said magnet pattern reflected about the x axis, or said magnet pattern reflected about the y axis, or said magnet pattern with the x and y axes transposed, where within the notation s(x,y), \u201cs\u201d indicates the respective component magnet strength and polarity and \u201c(x,y)\u201d indicates x and y coordinates of a center of the respective component magnet relative to a reference position (0,0).
10. The magnetic field force generator as recited in claim 1, wherein the first pattern is a random or pseudorandom code.
11. The magnetic field force generator as recited in claim 10, wherein the pseudorandom code is a linear feedback shift register code.
12. The magnetic field force generator as recited in claim 10, wherein the pseudorandom code is a Barker code.
13. The magnetic field force generator as recited in claim 10, wherein the pseudorandom code is a Gold code.
14. The magnetic field force generator as recited in claim 10, wherein the pseudorandom code is a Kasami code.
15. The magnetic field force generator as recited in claim 10, wherein the pseudorandom code is a Golomb ruler code.
16. The magnetic field force generator as recited in claim 10, wherein the pseudorandom code is a Costas array.
17. The magnetic field force generator as recited in claim 10, wherein the random or pseudorandom code defines a magnet spacing pattern.
18. The magnetic field force generator as recited in claim 17, wherein the pseudorandom code is a Golomb ruler sequence.
19. The magnetic field force generator as recited in claim 17, wherein the first magnet structure includes at least one additional component magnet.
20. The magnetic field force generator as recited in claim 17, wherein the pseudorandom code is a Costas array.