1. A memory module comprising:
memory for storing data; and
multiple, independent data channels communicatively coupled to said memory.
2. The memory module of claim 1 wherein said memory module comprises a dual in-line memory module (DIMM).
3. The memory module of claim 1 wherein said memory for storing data comprises at least one dynamic random access memory (DRAM).
4. The memory module of claim 3 wherein said memory comprises a plurality of separate DRAMs, and wherein each of the multiple, independent data channels provides access to a different one of the plurality of separate DRAMs.
5. The memory module of claim 1 wherein each of the multiple, independent data channels provides access to a different portion of said memory.
6. The memory module of claim 1 wherein the multiple, independent data channels are operable to carry data for independent memory access operations.
7. The memory module of claim 6 wherein the multiple, independent data channels comprise:
eight 8-bit wide data channels.
8. The memory module of claim 7 wherein, for a respective independent memory access operation being serviced by one of the eight data channels, the one data channel carries data in a burst of 8 time units, thereby carrying 8 bytes of data for servicing the respective independent memory access operation.
9. The memory module of claim 1 wherein each of the multiple, independent data channels is operable to carry a sub-cache-block of data for independent memory access operations.
10. The memory module of claim 9 wherein, over a time period for carrying a cache-block of data, the multiple, independent data channels each carry a sub-cache-block of data.
11. The memory module of claim 10 wherein each of the multiple, independent data channels carries said sub-cache-block of data for servicing a different, independent memory access operation.
12. The memory module of claim 11 wherein the time period for carrying said cache-block of data comprises an 8 time unit burst of 64-bytes of data.
13. The memory module of claim 12 wherein the 8 time unit burst comprises either 8 clock cycles or 8 clock phases.
14. The memory module of claim 12 wherein during said 8 time unit burst said multiple, independent data channels each carries 8-bytes of data for a different one of eight independent memory access operations.
15. The memory module of claim 1 further comprising:
control logic for receiving address and control information for a plurality of independent memory access operations to be serviced by the multiple, independent data channels.
16. The memory module of claim 15 wherein the control logic receives the address and control information from an external memory controller via an addresscontrol channel.
17. The memory module of claim 15 wherein the received address and control information comprises row select and column access commands encoded into a single command.
18. The memory module of claim 17 wherein dual data rate (DDR) signaling is employed for the received address and control information.
19. The memory module of claim 17 further comprising:
a plurality of internal addresscontrol channels for carrying address and control information for the multiple, independent data channels, wherein the control logic is operable to decode the received address and control information to result in address and control information for the plurality of internal addresscontrol channels.
20. The memory module of claim 19 wherein the plurality of internal addresscontrol channels comprise four independent internal addresscontrol channels.
21. The memory module of claim 20 wherein the multiple, independent data channels comprise eight independent data channels, and wherein each of the four independent internal addresscontrol channels carries address and control information for two of the eight independent data channels.
22. A memory module comprising:
memory for storing data;
a plurality of independent data channels for accessing said memory;
a plurality of internal addresscontrol channels for carrying address and control information for the plurality of independent data channels; and
control logic operable to receive encoded address and control information, and decode the received address and control information to result in address and control information for the plurality of internal addresscontrol channels.
23. The memory module of claim 22 wherein each of the plurality of independent data channels is operable to service an independent memory access operation as specified by the decoded address and control information on the internal addresscontrol channels.
24. The memory module of claim 22 wherein the decoded address and control information specifies a plurality of independent memory access operations, and wherein the plurality of independent data channels each carries data for a separate one of the plurality of independent memory access operations.
25. The memory module of claim 22 wherein said memory comprises a plurality of separate memories, and wherein each of the plurality independent data channels provides access to a different one of the plurality of separate memories.
26. The memory module of claim 25 wherein each of the plurality of separate memories comprises a dynamic random access memory (DRAM).
27. The memory module of claim 22 wherein said memory module comprises a dual in-line memory module (DIMM).
28. The memory module of claim 22 wherein the plurality of independent data channels comprise:
eight 8-bit wide data channels.
29. The memory module of claim 28 wherein, for a respective independent memory access operation being serviced by one of the eight data channels, the one data channel carries data in a burst of 8 time units, thereby carrying 8 bytes of data for servicing the respective independent memory access operation.
30. The memory module of claim 22 wherein each of the plurality of independent data channels is operable to carry a sub-cache-block of data for independent memory access operations.
31. The memory module of claim 30 wherein, over a time period for carrying a cache-block of data, the plurality of independent data channels each carry a sub-cache-block of data.
32. The memory module of claim 31 wherein, over the time period for carrying the cache-block of data, the plurality of independent data channels carry in aggregate a cache-block of data.
33. The memory module of claim 31 wherein each of the plurality of independent data channels carries said sub-cache-block of data for servicing a different independent memory access operation.
34. The memory module of claim 33 wherein the time period for carrying said cache-block of data comprises an 8 time unit burst of 64-bytes of data.
35. The memory module of claim 34 wherein the 8 time unit burst comprises either 8 clock cycles or 8 clock phases.
36. The memory module of claim 34 wherein during said 8 time unit burst said plurality of independent data channels each carries 8-bytes of data for a different one of eight independent memory access operations.
37. The memory module of claim 22 wherein the received encoded address and control information comprises row select and column access commands encoded into a single command.
38. The memory module of claim 37 wherein dual data rate (DDR) signaling is employed for the received encoded address and control information.
39. The memory module of claim 22 wherein the plurality of internal addresscontrol channels comprise four independent internal addresscontrol channels.
40. The memory module of claim 39 wherein the plurality of independent data channels comprise eight independent data channels, and wherein each of the four independent internal addresscontrol channels carries address and control information for two of the eight independent data channels.
41. The memory module of claim 22 wherein the control logic comprises a field-programmable gate array (FPGA).
42. The memory module of claim 22 wherein the control logic comprises an application-specific integrated circuit (ASIC).
43. A memory module comprising:
memory for storing data; and
a plurality of independent data channels communicatively coupled to said memory, wherein each of the plurality of independent data channels is operable to carry a sub-cache-block of data for independent memory access operations.
44. The memory module of claim 43 wherein, over a time period for carrying a cache-block of data, the plurality of independent data channels each carry said sub-cache-block of data.
45. The memory module of claim 44 wherein, over the time period for carrying the cache-block of data, the plurality of independent data channels carry in aggregate a cache-block of data.
46. The memory module of claim 44 wherein each of the plurality of independent data channels carries said sub-cache-block of data for servicing a different, independent memory access operation.
47. The memory module of claim 46 wherein the time period for carrying said cache-block of data comprises an 8 time unit burst of 64-bytes of data.
48. The memory module of claim 47 wherein the 8 time unit burst comprises either 8 clock cycles or 8 clock phases.
49. The memory module of claim 47 wherein during said 8 time unit burst said plurality of independent data channels each carries 8-bytes of data for a different one of eight independent memory access operations.
50. A method of servicing memory access requests, the method comprising:
receiving, at a memory module, via an external addresscontrol channel, encoded address and control information for a plurality of independent memory access operations;
decoding, by control logic of the memory module, the received encoded address and control information into information for a plurality of internal independent addresscontrol channels within the memory module; and
carrying data for servicing the plurality of independent memory access operations as defined by the information on the plurality of internal independent addresscontrol channels via a plurality of independent data channels of the memory module.
51. The method of claim 50 wherein each of the plurality of independent data channels is operable to carry a sub-cache-block of data for a corresponding one of the plurality of independent memory access operations.
52. The method of claim 51 wherein said carrying comprises:
over a time period for carrying a cache-block of data, the plurality of independent data channels each car y said sub-cache-block of data.
53. The method of claim 52 wherein said carrying comprises:
over the time period for carrying the cache-block of data, the plurality of independent data channels carry in aggregate a cache-block of data.
54. The method of claim 52 wherein the time period for carrying said cache-block of data comprises an 8 time unit burst of 64-bytes of data.
55. The memory module of claim 54 wherein during said 8 time unit burst said plurality of independent data channels each carries 8-bytes of data for a different one of eight independent memory access operations.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A vehicle behavior control apparatus comprising:
a steering angle detection means for detecting a steering angle of a vehicle;
a lateral acceleration detection means for detecting a lateral acceleration of the vehicle;
a yaw rate detection means for detecting an actual yaw rate of the vehicle; and
a control section for controlling a behavior of the vehicle according to output values outputted from the steering angle detection means and the yaw rate detection means, wherein
the control section includes:
a first turning direction estimating means for estimating a first yaw rate according to the output value of the steering angle detection means and estimating a first turning direction from positive and negative of the first yaw rate when an absolute value of the first yaw rate concerned is not less than a first threshold value;
a second turning direction estimating means for estimating a second yaw rate according to an output value of the lateral acceleration detection means and estimating a second turning direction from positive and negative of a difference between the second yaw rate and a second threshold value when the second yaw rate is not less than or not more than the second threshold value;
a vehicle turning direction judging means for judging that the direction when the first turning direction and the second turning direction are the same is a turning direction of the vehicle; and
an abnormality judging means for judging that the yaw rate detection means is abnormal when the turning direction of the vehicle and the direction of the actual yaw rate are different from each other.
2. The vehicle behavior control apparatus according to claim 1, wherein the second turning direction estimating means sets the second yaw rate, which is a yaw rate at the time when an absolute value of the first yaw rate exceeds the first threshold value, to be the second threshold value.
3. The vehicle behavior control apparatus according to claim 1, wherein the abnormality judging means judges an abnormality of the yaw rate detection means when a predetermined period of time has passed from a point of time when it is judged that the turning direction of the vehicle and the direction of the actual yaw rate are different from each other.
4. The vehicle behavior control apparatus according to claim 1, wherein the direction of the actual yaw rate is a direction estimated from positive and negative of the output value of the yaw rate detection means.
5. The vehicle behavior control apparatus according to claim 1, wherein the direction of the actual yaw rate is a direction estimated from positive and negative of a difference between the output value right before the output value of the yaw rate detection means shows a change by a value not less than the third threshold value and the output value after the output value of the yaw rate detection means has changed by a value not less than the third threshold value.
6. A vehicle behavior control apparatus comprising:
a steering angle detection unit which detects a steering angle of a vehicle;
a lateral acceleration detection unit which detects a lateral acceleration of the vehicle;
a yaw rate detection unit which detects an actual yaw rate of the vehicle; and
a control section which controls a behavior of the vehicle according to output values outputted from the steering angle detection unit and the yaw rate detection unit, wherein
the control section includes:
a first turning direction estimating unit which estimates a first yaw rate according to the output value of the steering angle detection unit and estimates a first turning direction from positive and negative of the first yaw rate when an absolute value of the first yaw rate concerned is not less than a first threshold value;
a second turning direction estimating unit which estimates a second yaw rate according to an output value of the lateral acceleration detection unit and estimates a second turning direction from positive and negative of a difference between the second yaw rate and a second threshold value when the second yaw rate is not less than or not more than the second threshold value;
a vehicle turning direction judging unit which judges that the direction when the first turning direction and the second turning direction are the same is judged to be a turning direction of the vehicle; and
an abnormality judging unit which judges that the yaw rate detection unit is abnormal when the turning direction of the vehicle and the direction of the actual yaw rate are different from each other.
7. The vehicle behavior control apparatus according to claim 6, wherein the second turning direction estimating unit sets the second yaw rate, which is a yaw rate at the time when an absolute value of the first yaw rate exceeds the first threshold value, to be the second threshold value.
8. The vehicle behavior control apparatus according to claim 6, wherein the abnormality judging unit judges an abnormality of the yaw rate detection unit when a predetermined period of time has passed from a point of time when it is judged that the turning direction of the vehicle and the direction of the actual yaw rate are different from each other.
9. The vehicle behavior control apparatus according to claim 6, wherein the direction of the actual yaw rate is a direction estimated from positive and negative of the output value of the yaw rate detection unit.
10. The vehicle behavior control apparatus according to claim 6, wherein the direction of the actual yaw rate is a direction estimated from positive and negative of a difference between the output value right before the output value of the yaw rate detection unit shows a change by a value not less than the third threshold value and the output value after the output value of the yaw rate detection unit has changed by a value not less than the third threshold value.