1. A SOI MOS device having body tied to source (BTS) structure comprises:
a semiconductor substrate;
a buried oxide layer (BOX) formed on the semiconductor substrate;
an active region formed on the buried oxide layer, including a gate region, a body region formed under the gate region, an N-type source region and an N-type drain region which are located on the two opposite ends of the body region, and an insulation spacer formed surrounding the gate region; and
an shallow trench isolation region formed surrounding the active region;
wherein the N-type source region comprises: two heavily doped N-type regions; a heavily doped P-type region formed between the two heavily doped N-type regions; a silicide formed on, which is also contact to, the two heavily doped N-type regions and the heavily doped P-type region; a shallow N-type region which is contact to the silicide; the heavily doped P-type region is contact to all of the two heavily doped N-type regions, the shallow trench isolation region, the body region and the silicide thereon.
2. A The SOI MOS device having body tied to source (BTS) structure in claim 1, wherein the silicide is made of the material selected from cobalt silicide or titanium silicide.
3. A The SOI MOS device having body tied to source (BTS) structure in claim 1, wherein the body region is made of the P-type Si material.
4. A method of manufacturing a SOI MOS device having body tied to source (BTS) structure comprises steps of:
(a) forming a shallow trench isolation structure on a Si material having a buried insulation layer to isolate a Si material region, and creating a gate region on the Si material region;
(b) performing source and drain light doping process to form a lightly doped N-type source region and a lightly doped N-type drain region;
(c) providing an insulation spacer around the gate region, wherein the insulation spacer covers part of the surfaces of the lightly doped N-type source region and the lightly doped N-type drain region, then forming an N-type Si material source region and an N-type drain region via source and drain ion implantation, and forming a body region between the N-type Si material source region and the N-type drain region; wherein the N-type Si material source region is composed of a shallow N-type region and a heavily doped N-type region which are located under the insulation spacer;
(d) implanting ions underneath from the part of the N-type Si material source region’s surface that is not covered by the insulation spacer via ion implantation to form a heavily doped P-type region in the middle of the heavily doped N-type region, wherein the heavily doped P-type region dividing the heavily doped N-type region into two heavily doped N-type regions located separately;
(e) forming a metal layer on the surface of the heavily doped P-type region and the two heavily doped N-type regions, and then allowing the reaction between the metal layer and the Si material underneath to form a silicide by heat treatment and proceeding the reaction until the silicide formed being contact to the heavily doped P-type region and the two heavily doped N-type regions; and an N-type source region being formed by the silicide, the heavily doped P-type region, two heavily doped N-type regions and the shallow N-type region.
5. The method of manufacturing a SOI MOS device having body tied to source (BTS) structure in claim 4, wherein in step (a), P-ion implantation in the Si material region isolated is performed firstly before creating the gate region.
6. The method of manufacturing a SOI MOS device having body tied to source (BTS) structure in claim 4, wherein in step (b), the implantation dose of the lightly source and drain region doping could reach the magnitude of 1e15cm2, and the concentration of the lightly doped N-type source region and the lightly doped N-type drain region could reach the magnitude of 1e19cm3.
7. The method of manufacturing a SOI MOS device having body tied to source (BTS) structure in claim 4, wherein in step (d), a mask with an opening thereon which is aligned with the edge of the insulation spacer in the middle of the heavily doped N-type region is adopted to perform heavily doped P ion implantation vertically to form a heavily doped P-type region.
8. The method of manufacturing a SOI MOS device having body tied to source (BTS) structure in claim 4, wherein in step (e), the metal layer is formed of the metal selected from Co or Ti.
9. The method of manufacturing a SOI MOS device having body tied to source (BTS) structure in claim 4, wherein in step (e), furnace annealing procedure is adopted in the heat treatment.
10. The method of manufacturing a SOI MOS device having body tied to source (BTS) structure in claim 4, wherein in step (e), the temperature of heat treatment is ranging from 700 to 900 and the time of the heat treatment is ranging from 50 seconds to 70 seconds.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a microelectronic device, the method comprising:
forming a mold layer on a semiconductor substrate wherein the mold layer includes a hole therein exposing a channel region of the semiconductor substrate;
after forming the mold layer, forming a gate dielectric layer on sidewalls of the hole and on the channel region of the semiconductor substrate wherein the gate dielectric layer comprises a high-k dielectric material;
forming a gate electrode barrier layer on the gate dielectric layer opposite the channel region and opposite sidewalls of the hole;
forming a gate electrode metal layer on the gate electrode barrier layer opposite the channel region and opposite sidewalls of the hole; and
after forming the gate electrode metal layer, removing the mold layer.
2. A method according to claim 1 wherein the gate electrode barrier layer and the gate electrode metal layer comprise different materials.
3. A method according to claim 1 wherein the high-k dielectric material comprises a high-k metal-oxide dielectric material.
4. A method according to claim 3 wherein the high-k metal-oxide dielectric material comprises at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, niobium oxide, cesium oxide, indium oxide, iridium oxide, Ba1-xSrxTiO3 (BST), andor Pb(Zr,Ti)O3 (PZT).
5. A method according to claim 1 wherein the gate electrode barrier layer comprises a material having a work function in the range of approximately 3.9eV to 4.4eV.
6. A method according to claim 1 wherein the gate electrode barrier layer comprises tantalum nitride.
7. A method according to claim 1 wherein the gate electrode metal layer comprises at least one of tungsten, tantalum, aluminum, titanium, copper, titanium silicide, cobalt silicide, andor alloys thereof.