1. A method for performing multisampling-based antialiasing in a system that includes a first graphics processing unit (GPU) and a second GPU comprising:
rendering a first version of a frame in the first GPU using a first multisampling pattern;
rendering a second version of the frame in the second GPU using a second multisampling pattern;
identifying edge pixels in the second version of the frame; and
combining pixels in the first version of the frame with only those pixels in the second version of the frame that have been identified as edge pixels to generate a combined frame.
2. The method of claim 1, wherein rendering the first version of the frame in the first GPU using the first multisampling pattern comprises:
sampling each pixel in the frame in accordance with the first multisampling pattern to obtain multiple first samples for each pixel; and
resolving the multiple first samples for each pixel to generate the pixels of the first version of the frame.
3. The method of claim 2, wherein rendering the second version of the frame in the second GPU using the second multisampling pattern comprises:
sampling each pixel in the frame in accordance with the second multisampling pattern to obtain multiple second samples for each pixel; and
resolving the multiple second samples for each pixel to generate the pixels of the second version of the frame.
4. The method of claim 1, wherein identifying edge pixels in the second version of the frame comprises:
accessing data indicating whether or not a pixel in the second version of the frame is compressed; and
if the accessed data indicates that the pixel in the second version of the frame is not compressed, identifying the pixel in the second version of the frame as an edge pixel.
5. The method of claim 1, wherein combining pixels in the first version of the frame with only those pixels in the second version of the frame that have been identified as edge pixels comprises:
generating a mask based on compression data associated with the pixels in the second version of the frame;
applying the mask to the second version of the frame; and
transferring only those pixels in the second version of the frame that are not covered by the mask over a bus for combination with the pixels in the first version of the frame.
6. The method of claim 1, wherein combining pixels in the first version of the frame with only those pixels in the second version of the frame that have been identified as edge pixels comprises:
linearly blending pixels in the first version of the frame with only those pixels in the second version of the frame that have been identified as edge pixels.
7. A graphics processing system, comprising:
a first graphics processing unit (GPU) configured to render a first version of a frame using a first multisampling pattern;
a second graphics processing unit (GPU) configured to render a second version of the frame using a second multisampling pattern; and
a bus connecting the first GPU and the second GPU;
wherein the second GPU is further configured to identify edge pixels in the second version of the frame and to transfer only those pixels in the second version of the frame that have been identified as edge pixels over the bus to the first GPU, and
wherein the first GPU is further configured to combine the pixels in the first version of the frame with the pixels transferred from the second GPU to generate a combined frame.
8. The system of claim 7, wherein the bus comprises a PCI-Express bus.
9. The system of claim 7, wherein the first GPU is configured to sample each pixel in the frame in accordance with the first multisampling pattern to obtain multiple first samples for each pixel and to resolve the multiple first samples for each pixel to generate the pixels of the first version of the frame.
10. The system of claim 9, wherein the second GPU is configured to sample each pixel in the frame in accordance with the second multisampling pattern to obtain multiple second samples for each pixel and to resolve the multiple second samples for each pixel to generate the pixels of the second version of the frame.
11. The system of claim 7, wherein the second GPU comprises:
a memory;
wherein the second GPU is further configured to access a table stored in the memory and to identify a pixel in the second version of the frame as an edge pixel if the table indicates that the pixel in the second version of the frame is not compressed.
12. The system of claim 7, wherein the second GPU is further configured to generate a mask based on compression data associated with the pixels in the second version of the frame, to apply the mask to the second version of the frame, and to transfer only those pixels in the second version of the frame that are not covered by the mask over the bus to the first GPU.
13. The system of claim 7, wherein the first GPU includes a compositor, the compositor configured to linearly blend pixels in the first version of the frame with the pixels transferred from the second GPU to generate the combined frame.
14. A method for identifying edge pixels in a rendered image that consists of a plurality of tiles, each of the plurality of tiles consisting of a plurality of pixels, the method comprising:
accessing data to determine whether a selected tile in the plurality of tiles is fully compressed;
identifying the selected tile as including only non-edge pixels responsive to a determination that the selected tile is fully compressed; and
identifying the selected tile as including one or more edge pixels responsive to a determination that the selected tile is not fully compressed.
15. The method of claim 14, wherein accessing data to determine whether or not the selected tile is fully compressed comprises:
accessing an entry in a table corresponding to the selected tile, wherein the entry indicates whether the selected tile is fully compressed, partially compressed, or uncompressed.
16. The method of claim 15, wherein accessing data to determine whether or not the selected block of pixels is fully compressed comprises further comprises:
resolving predefined multisample pixel data in accordance with the entry in the table to generate a resolved tile; and
determining whether or not the selected tile is fully compressed based on one or more color values associated with pixels in the resolved tile.
17. A computer program product comprising a tangible computer useable medium having control logic stored therein, the control logic for causing a graphics processor to identify edge pixels in a rendered image that consists of a plurality of tiles, each of the plurality of tiles consisting of a plurality of pixels, the control logic comprising:
first computer readable program code means for causing the graphics processor to access data to determine whether a selected tile in the plurality of tiles is fully compressed;
second computer readable program code means for causing the graphics processor to identify the selected tile as including only non-edge pixels responsive to a determination that the selected tile is fully compressed; and
third computer readable program code means for causing the graphics processor to identify the selected tile as including one or more edge pixels responsive to a determination that the selected tile is not fully compressed.
18. The computer program product of claim 17, wherein the first computer readable program code means comprises:
means for causing the graphics processor to access an entry in a table corresponding to the selected tile, wherein the entry indicates whether the selected tile is fully compressed, partially compressed, or uncompressed.
19. The computer program product of claim 18, wherein the first computer readable program code means further comprises:
means for causing the graphics processor to resolve predefined multisample pixel data in accordance with the entry in the table to generate a resolved tile; and
means for causing the graphics processor to determine whether or not the selected tile is fully compressed based on a color value associated with pixels in the resolved tile.
20. A method for performing multisampling-based antialiasing in a system that includes a first graphics processing unit (GPU) and a second GPU comprising:
rendering a first version of a frame in the first GPU using a first multisampling pattern;
rendering edge pixels associated with a second version of a frame in the second GPU using a second multisampling pattern;
transferring the edge pixels from the second GPU to the first GPU; and
combining the edge pixels transferred from the second GPU with pixels in the first version of the frame to generate a combined frame.
21. A computer program product comprising a tangible computer useable medium having control logic stored therein, the control logic for causing a first graphics processing unit (GPU) and a second GPU to performing multisampling-based antialiasing, the control logic comprising:
first computer readable program code means for causing the first GPU to render a first version of a frame in using a first multisampling pattern;
second computer readable program code means for causing a second GPU to render a second version of the frame using a second multisampling pattern;
third computer readable program code means for causing the second GPU to identify edge pixels in the second version of the frame; and
fourth computer readable program code means for causing the first GPU andor the second GPU to combine pixels in the first version of the frame with only those pixels in the second version of the frame that have been identified as edge pixels to generate a combined frame.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An interconnect device comprising:
a support formed by several superimposed substrates andor layers in which at least one hole is formed, the hole having walls forming a closed contour and being formed by a cavity and one or several slots communicating with the cavity, the cavity is formed by a first opening made in a first substrate and a second opening, with a different cross-sectional area from the first opening and made in a second substrate, the one or several slots extending over all or part of the length of the hole, one or several conducting elements being positioned on at least one wall of the hole and passing through the hole, the one or several conducting elements each being intended to connect conducting areas to each other situated on either side of the support,
wherein at least one of the one or several conducting elements is housed in one of said one or several slots and covers less than an entire surface of said one of said one or several slots.
2. The interconnect device according to claim 1, wherein at least one of said one or several slots separates two of said several conducting elements from each other.
3. The interconnect device according to claim 1, wherein at least one of the one or several conducting elements extends along said one of said one or several slots.
4. The interconnect device according to claim 1, wherein the cavity passes through the thickness of the support.
5. The interconnect device according to claim 1, wherein the bottom of the cavity is blind.
6. The interconnect device according to claim 1, wherein said one or several slots communicate with said first opening, and one or several other slots formed in the second substrate along the cavity formed in said substrate communicate with the second opening.
7. The interconnect device according to claim 1, wherein the walls of the cavity are covered with conducting material.
8. A method for making an interconnect device according to claim 1, comprising:
forming conducting pads passing through the support; and
forming the cavity in the thickness of the support so as to open and remove part of the conducting pads, the other part of the conducting pads being kept and forming conducting elements housed in grooves.
9. A method for making an interconnect device according to claim 1, comprising:
forming the cavity in the thickness of the support;
forming an area with a conducting base covering the walls of the cavity; and
forming at least one slot so as to open the conducting material, the slot communicating with the cavity.
10. A method for making an interconnect device according to claim 1, comprising:
forming the cavity in the thickness of the support and slots communicating with said cavity and extending over all or part thereof;
forming a layer of sacrificial material in the slots, so as to separate the slots from the cavity;
forming a conducting layer on the walls of the cavity; and
removing the layer of sacrificial material so as to remove portions of the conducting layer between the slots and the cavity.
11. A method for making an interconnect device according to claim 1, comprising:
forming the cavity in the thickness of the support;
forming at least one slot communicating with said cavity and extending over all or part thereof, said slot being made to have, in a plane parallel to the support, a variable section with a narrowing at the connection between the slot and the cavity; and
performing a directional deposition of conducting material on said wall and on part of the slot.
12. An interconnect device comprising:
a support in which at least one hole is formed, the hole having walls forming a closed contour and being formed by a cavity and one or several recessed slots in the walls and communicating with the cavity, the one or several slots extending over all or part of the length of the hole, one or several conducting elements being intended to connect conducting areas to each other situated on either side of the support, and the one or several conducting elements covering, inside the hole, at least part of the walls of the cavity and only a portion of an inside of the slots, the slots ensuring an electrical discontinuity between conducting elements in the slots and conducting elements of the cavity.
13. The interconnect device according to claim 12, wherein the cavity passes through the thickness of the support.
14. The interconnect device according to claim 12, wherein the cavity is formed by a blind orifice formed in the support.
15. The interconnect device according to claim 12, wherein the support is formed by several superimposed substrates andor layers.
16. The interconnect device according to claim 12, wherein the support is formed by several superimposed substrates andor layers, and the cavity is formed by a first opening made in a first substrate and a second opening with a section different from the first opening and made in a second substrate.
17. The interconnect device according to claim 16, wherein the bottom of the cavity is blind, said one or several slots communicate with said first opening, and one or several other slots formed in the second substrate along the cavity formed in said substrate communicate with the second opening.
18. A method for making an interconnect device according to claim 12, comprising the steps consisting of:
a. forming a cavity in the thickness of the support,
b. forming at least one slot communicating with said cavity and extending over all or part thereof, said slot being made such that it has, in a plane parallel to the support, a variable section with a narrowing at the connection between the slot and the cavity,
c. performing a directional deposition of conducting material on said wall and on part of the slot.