1. A water purification system, comprising:
a base composed of flexible material and forming a reservoir for holding raw water;
a gutter forming a channel;
a cover composed of flexible material and coupled to the base, the cover positioned at an incline such that raw water evaporated from the reservoir condenses on an inner surface and is pulled by gravity to the channel; and
a collapsible frame for supporting the base and cover,
wherein the gutter is positioned within an evaporation chamber formed by the base and the cover.
2. The system of claim 1, wherein the frame comprises a plurality of support elements and a sleeve, wherein each of the support elements is inserted into the sleeve.
3. The system of claim 1, wherein the frame comprises:
a first sleeve;
a second sleeve;
a first support element inserted into the first sleeve;
a second support element inserted into the second sleeve; and
a third support element inserted into the first and second sleeves.
4. The system of claim 3, further comprising a third sleeve coupled to the base, wherein the third support element passes through the third sleeve.
5. The system of claim 3, wherein each of the support elements comprises a pole.
6. The system of claim 3, wherein each of the support elements comprises a polyvinyl chloride (PVC) pipe.
7. The system of claim 1, wherein the cover is transparent.
8. The system of claim 1, further comprising an absorbing pad for absorbing the raw water, wherein the absorption pad is positioned in the reservoir.
9. The system of claim 1, wherein the gutter is attached to an inner surface of the cover at a plurality of points.
10. The system of claim 9, wherein an end of the gutter is coupled to a weight.
11. A water purification method, comprising:
coupling a base to a cover of a water purification system, the base composed of a flexible material and the cover composed of a flexible material, the base and the cover forming an evaporation chamber;
inserting raw water into a reservoir formed by the base such that the raw water evaporates and condenses on an inner surface of the cover within the evaporation chamber;
positioning the cover at an incline such that gravity pulls the condensed water along the inner surface to a channel formed by a gutter that is within the evaporation chamber; and
coupling the base to a collapsible frame.
12. The method of claim 11, further comprising:
inserting a first support element of the frame into a first sleeve;
inserting a second support element of the frame into a second sleeve; and
inserting a third support element into the first and second sleeves.
13. The method of claim 12, further comprising inserting the third support element through a third sleeve that is coupled to the base.
14. The method of claim 11, wherein the cover is transparent.
15. The method of claim 11, wherein the gutter is attached to an inner surface of the cover at a plurality of points.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A mold die for molding a semiconductor device package comprising:
a cavity block, the cavity block including a concave surface defining a cavity in which a semiconductor chip may be positioned, the semiconductor chip being generally rectangular and having a top surface and bottom surface and four side surfaces;
a gate, the gate defining a mold resin entry into the cavity and having a gate width; and
a gate block arranged and configured for movement relative the cavity block to provide selective opening and closing of the gate,
wherein the gate is arranged relative to the semiconductor chip whereby mold resin entering the cavity through the gate will contact the side surfaces of the semiconductor chip at an angle of less than about 70.
2. A mold die for molding a semiconductor device package according to claim 1, wherein:
the cavity defined in the cavity block is substantially rectangular and has side walls;
the semiconductor chip is oriented with the side surfaces generally parallel to closest side wall of the cavity.
3. A mold die for molding a semiconductor device package according to claim 1, wherein:
the cavity defined in the cavity block has four side wall segments and three corners defining a first portion of a cavity perimeter;
the semiconductor chip being oriented with the side surfaces generally parallel to the closest side wall segments; and
the gate block, when closed, forms a second portion of the cavity perimeter.
4. The mold die for molding a semiconductor device package according to claim 1, wherein:
the cavity perimeter is substantially rectangular when the gate block is closed.
5. The mold die for molding a semiconductor device package according to claim 3, wherein:
the gate block includes an internal surface that provides the second portion of the cavity perimeter, the internal surface being positioned between a first side wall segment and a second side wall segment defined by the cavity block, and
further wherein the internal surface includes an inclined portion that is not parallel to the first or the second side wall segments.
6. The mold die for molding a semiconductor device package according to claim 5, wherein:
the internal surface further includes a first portion that is substantially parallel to the first side wall segment and a second portion that is substantially parallel to the second side wall segment.
7. The mold die for molding a semiconductor device package according to claim 5, wherein:
the internal surface is substantially identical to the inclined portion of the internal surface, the gate width is substantially identical to a length of the inclined portion.
8. The mold die for molding a semiconductor device package according to claim 3, wherein:
a third side wall segment is positioned opposite and generally parallel to the first side wall segment, the third side wall segment being longer than the first side wall segment;
a fourth side wall segment is positioned opposite and generally parallel to the second side wall segment, the fourth side wall segment being longer than the second side wall segment; and
the gate width is at least equal to one-half of a first length equal to the shorter of the third and fourth side wall segments and is less than second length equal to the longer of the third and fourth side wall segments.
9. The mold die for molding a semiconductor device package according to claim 8, wherein:
the internal surface is symmetric about an axis extending from a corner of the cavity opposite the gate and extending through a center point of the cavity.
10. A mold die for molding a chip array package comprising:
a cavity block, the cavity block including a concave surface defining a cavity in which a plurality of semiconductor chips may be positioned, the semiconductor chips being generally rectangular and having a top surface and bottom surface and four side surfaces;
a gate, the gate defining a mold resin entry into the cavity and having a gate width; and
a gate block arranged and configured for movement relative the cavity block to provide selective opening and closing of the gate,
wherein the gate is arranged relative to the semiconductor chips whereby mold resin entering the cavity through the gate will contact the side surfaces of the semiconductor chips at an angle of less than about 70.
11. A mold die for molding a chip array package according to claim 10, wherein:
at least two of the plurality of semiconductor chips are arranged in a stacked orientation with bonding wires providing electrical connection between an upper semiconductor chip and a lower semiconductor chip.
12. A molding apparatus for molding a chip array comprising:
a mold die according to claim 1 wherein the cavity is arranged and configured to receive a plurality of aligned semiconductor chips having side surfaces, and further wherein the gate is arranged and configured so that mold resin entering the cavity through the gate will approach the side surfaces;
a pot for maintaining mold resin;
a channel block defining a fluid path between the pot and the gate block.
13. A molding apparatus for molding a plurality of chip arrays comprising:
a plurality of mold dies according to claim 1;
a pot for maintaining mold resin;
a channel block defining a plurality of fluid paths between the pot and the plurality of mold dies.
14. A method for molding a semiconductor device package using a mold die according to claim 1 comprising:
arranging a semiconductor chip within the cavity, the semiconductor chip having side surfaces;
moving the gate block to open a gate into the cavity;
injecting a flow of mold resin into the cavity through the gate to fill the cavity;
moving the gate block to close the gate;
solidifying the mold resin within the cavity to form the semiconductor device package; and
removing the semiconductor device package from the cavity,
wherein the gate is configured and positioned such that the flow of mold resin approaches the side surfaces at an angle of less than 90.
15. A method for molding a semiconductor device package using a mold die according to claim 1 comprising:
arranging a semiconductor chip within the cavity, the semiconductor chip having side surfaces and a plurality of bonding wires arranged adjacent the side surfaces for providing electrical connection between the semiconductor chip and a substrate;
moving the gate block to open a gate into the cavity;
injecting a flow of mold resin into the cavity through the gate to fill the cavity;
moving the gate block to close the gate;
solidifying the mold resin within the cavity to form the semiconductor device package; and
removing the semiconductor device package from the cavity,
wherein the gate is configured and positioned such that the mold resin flows past all bonding wires adjacent a single side surface of the semiconductor chip in a generally uniform direction.
16. A method for molding a semiconductor device package using a mold die according to claim 15 comprising:
arranging a semiconductor chip within the cavity, the semiconductor chip having side surfaces and a plurality of bonding wires arranged adjacent the side surfaces for providing electrical connection between the semiconductor chip and a substrate, wherein the bonding wires are arranged so as to provide a region of low bonding wire density adjacent a first corner of the semiconductor chip;
wherein the gate is configured and positioned such that the mold resin separates into two flows as it reaches a second corner of the semiconductor chip, the second corner being located diagonally across the semiconductor chip from the first corner, the two mold resin flows recombining near the region of low bonding wire density.