1. An apparatus comprising:
a vacuum chamber containing a particle detecting integrated circuit, the particle detecting integrated circuit including a plurality of devices, each of the plurality of devices including a pair of conductive lines that are configured to define a channel to capture at least one particle having an associated diameter, the pair of conductive lines of each of the plurality of devices includes a uniform pitch representing a single particle size between pairs.
2. The apparatus of claim 1 further comprising a computer system linked to the particle detecting integrated circuit.
3. The apparatus of claim 1 wherein the particle detecting integrated circuit includes a remote-controlled movable cover protecting the plurality of devices.
4. The apparatus of claim 2 wherein the computer system is configured to detect a change in current when a metallic particle shorts the exposed conductive lines of one of the plurality of devices.
5. The apparatus of claim 2 wherein the computer system is configured to detect a change in capacitance when a non-metallic particles lodges on or between the exposed conductive lines of one of the plurality of devices.
6. An apparatus comprising:
a mask stage in a vacuum chamber of semiconductor processing equipment;
a particle detecting integrated circuit embedded in the mask stage, the particle detecting integrated circuit comprising a plurality of devices, each of the plurality of devices having a pair of conductive lines exposed to a local vacuum environment, the pair of conductive lines are configured to define a channel to capture at least one particle having an associated diameter, the pair of conductive lines of each of the plurality of devices having a uniform pitch representing a single particle size.
7. The apparatus of claim 6 further comprising a computer system linked to the particle detecting integrated circuit.
8. The apparatus of claim 7 wherein the pair of conductive lines of each of the plurality of configured to have an applied voltage.
9. The apparatus of claim 8 wherein the computer system is configured to detect a change in current when a metallic particle shorts the pair of conductive lines of one of the plurality of devices.
10. The apparatus of claim 8 wherein the computer system is configured to detect a change capacitance when a non-metallic particle lodges on or between the pair of conductive lines of one of the plurality of devices of the particle detecting integrated circuit.
11. An apparatus comprising;
a vacuum chamber containing a particle detecting integrated circuit, the particle detecting integrated circuit including a plurality of devices, each of the plurality of devices including a pair of conductive lines that are configured to define a channel to capture at least one particle having an associated diameter, the pair of conductive lines of each of the plurality of devices includes one of a plurality of pitches representing a range of particle sizes between pairs.
12. The apparatus of claim 11 further comprising a computer system linked to the particle detecting integrated circuit.
13. The apparatus of claim 11 wherein the particle detecting integrated circuit includes a remote-controlled movable cover protecting the plurality of devices.
14. The apparatus of claim 12 wherein the computer system is configured to detect a change in current when a metallic particle shorts the exposed conductive lives of one of the plurality or devices.
15. The apparatus of claim 12 wherein the computer system is configured to detect a change in capacitance when a non-metallic particles lodges on or between the exposed conductive lines of one of the plurality of devices.
16. An apparatus comprising:
a mask stage in a vacuum chamber of semiconductor processing equipment;
a particle detecting integrated circuit embedded in the mask stage, the particle detecting integrated circuit comprising a plurality of devices, each of the plurality of devices having a pair of conductive lines exposed to a local vacuum environment, the pair of conductive lines are configured to define, a channel to capture at least one particle having an associated diameter, the pair of conductive line of each of the plurality of devices having a non-uniform pitch representing a range of particle sizes.
17. The apparatus of claim 16 further comprising a computer system linked to the particle detecting integrated circuit.
18. The apparatus of claim 17 wherein the pair of conductive lines of each of the plurality of devices is configured to have an applied voltage.
19. The apparatus of claim 18 wherein the computer system is configured to detect a chance in current when a metallic particle shorts one of the pairs of conductive lines.
20. The apparatus of claim 18 wherein the computer system is configured to detect a change in capacitance when a non-metallic particle lodges on or between the pair of conductive lines of one of the plurality of devices of the particle detecting integrated circuit.
21. The apparatus of claim 17 wherein the computer system is semiconductor component circuitry.
22. The apparatus of claim 17 wherein the computer system is off-chip circuitry.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit for generating a clock of a semiconductor memory apparatus, the circuit comprising:
a reference voltage generator configured to generate a reference voltage;
a reference current generator configured to generate a reference current having a constant current value regardless of a change in temperature; and
an oscillator configured to receive the reference voltage and the reference current to generate a clock that has constant frequency.
2. The circuit of claim 1,
wherein the oscillator is configured to generate the clock using charging and discharging times of a capacitor.
3. The circuit of claim 2,
wherein the oscillator is configured to generate the clock by providing the reference current to the capacitor to accumulate electric charges in the capacitor and discharging the capacitor when a level of the voltage accumulated in the capacitor is higher than that of the reference voltage.
4. The circuit of claim 1,
wherein the oscillator comprises:
an electric charge charging unit comprising a first capacitor and a second capacitor;
a comparing unit configured to compare a voltage level of the reference voltage with a voltage level of a voltage stored in the first capacitor and a voltage level of a voltage stored in the second capacitor so as to generate a first comparison signal and a second comparison signal, respectively;
a control signal generating unit configured to generate a first control signal and a second control signal in response to the first comparison signal and the second comparison signal, respectively; and
a control unit configured to receive the first control signal and the second control signal to control the charging and discharging of the first capacitor and the second capacitor.
5. The circuit of claim 4,
wherein the comparing unit comprises:
a first comparator configured to compare the voltage stored in the first capacitor with the reference voltage to generate the first comparison signal; and
a second comparator configured to compare the voltage stored in the second capacitor with the reference voltage to generate the second comparison signal.
6. The circuit of claim 4,
wherein the control signal generating unit is configured to determine a logic level of the first control signal and a logic level of the second control signal according to a logic level of the first comparison signal and a logic level of the second comparison signal.
7. The circuit of claim 6,
wherein the control signal generating unit is configured to output the first control signal and the second control signal, the first and second control signals having different logic levels from each other.
8. The circuit of claim 7,
wherein the control signal generating unit comprises a comparator configured to receive the first comparison signal and the second comparison signal to output the first control signal and the second control signal.
9. The circuit of claim 4,
wherein the control unit is configured to receive the reference current, the first control signal, and the second control signal to control the first and second capacitors.
10. The circuit of claim 9,
wherein the control unit comprises:
a first capacitor control unit configured to charge the first capacitor by outputting the reference current according to the first control signal or to discharge the first capacitor by connecting the first capacitor to a ground terminal; and
a second capacitor control unit configured to charge the second capacitor by outputting the reference current according to the second control signal or to discharge the second capacitor by connecting the second capacitor to a ground terminal.
11. The circuit of claim 10,
wherein the first capacitor control unit comprises:
a charging unit configured to output the reference current in response to the first control signal; and
a discharging unit configured to control a connection status of the ground terminal in response to the first control signal.
12. The circuit of claim 11,
wherein the charging unit and the discharging unit comprise transistors.
13. The circuit of claim 10,
wherein the second capacitor control unit comprises:
a charging unit configured to output the reference current in response to the second control signal; and
a discharging unit configured to control a connection status of the ground terminal in response to the second control signal.
14. The circuit of claim 13,
wherein the charging unit and the discharging unit comprise transistors.
15. The circuit of claim 10,
wherein when the first capacitor control unit is configured to charge the first capacitor, the second capacitor control unit is configured to discharge the second capacitor, and when the first capacitor control unit discharges the first capacitor, the second capacitor control unit charges the second capacitor.
16. The circuit of claim 1,
wherein the reference voltage generator is configured to generate the reference voltage that is not affected by a change in temperature using a positive temperature coefficient voltage having a voltage level increase when the temperature increases and a negative temperature coefficient voltage having a voltage level decrease when the temperature increases.
17. The circuit of claim 16,
wherein the reference current generator comprises:
a first converting unit configured to convert the positive temperature coefficient voltage into a positive temperature coefficient current; and
a second converting unit configured to convert the negative temperature coefficient voltage into a negative temperature coefficient current, and
wherein the reference current is output from a node at which output terminals of the first converting unit and the second converting unit are connected to each other.
18. The circuit of claim 17,
wherein the first converting unit comprises a transistor comprising a gate terminal to which the positive temperature coefficient voltage is applied, a source terminal to which an external voltage is applied, and a drain terminal which is the output terminal of the first converting unit.
19. The circuit of claim 17,
wherein the second converting unit comprises a transistor comprising a gate terminal to which the negative temperature coefficient voltage is applied, a source terminal to which the external voltage is applied, and a drain terminal which is the output terminal of the second converting unit.
20. The circuit of claim 1, further comprising:
a control signal generator configured to determine a current value of the reference current by controlling the reference current generator.
21. The circuit of claim 20,
wherein the control signal generator is configured to generate a plurality of current control signals.
22. The circuit of claim 21,
wherein whether the plurality of current control signals generated by the control signal generator are activated or not is determined according to connection statuses of fuses.
23. The circuit of claim 20,
wherein the reference current generator comprises:
a plurality of fixed current generating units, each of which is configured to receive the positive temperature coefficient voltage and the negative temperature coefficient voltage of the reference voltage generator to generate a fixed current that has a constant current value regardless of temperature; and
a plurality of switching units configured to control the output of the fixed current in response to the plurality of current control signals, the switching units comprising output terminals that are connected in common to output the reference current.
24. The circuit of claim 23,
wherein each of the fixed current generating units comprises:
a first transistor comprising a drain terminal, a gate terminal to which the positive temperature coefficient voltage is applied and a source terminal to which the external voltage is applied; and
a second transistor comprising a gate terminal to which the negative temperature coefficient voltage is applied, a source terminal to which the external voltage is applied, and a drain terminal connected to the drain terminal of the first transistor.