1. An assembly for conducting liquid across a portion of a substrate, comprising:
a transistor and a heat transducer carried on the substrate and adapted for instantaneously vaporizing an amount of liquid;
a trench etched into the substrate for conducting the liquid; and
a mask layer substantially surrounding the trench and comprising a layer selected from a group of layers that includes an oxide layer that also forms part of the gate of the transistor and a passivation layer that also covers part of the heat transducer.
2. The assembly of claim 1 wherein the mask layer is the oxide layer that is covered with the passivation layer near but spaced slightly from the trench.
3. The assembly of claim 1 wherein the mask layer is the passivation layer and wherein the passivation layer is covered with a metal layer.
4. The assembly of claim 3 wherein a layer of phosphosilicate glass underlies the passivation layer at locations near but spaced slightly from the trench.
5. The assembly of claim 4 wherein the passivation layer includes silicon nitride and silicon carbide.
6. The assembly of claim 1 including a cartridge to which the assembly is connected, the cartridge supplying liquid to the assembly.
7. An assembly, comprising:
a substrate;
at least one drop generator for ejecting drops of ink from the substrate;
a layer configured to serve as a component of drop generator and as a mask to define the boundaries of at least one trench; and
at least one trench etched within the boundaries, the at least one trench configured for moving ink across the substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a substrate having a gate structure;
a first recess in a region of the substrate adjacent to the gate structure, wherein the recess includes a first side adjacent to the gate, a second side opposing the first side and a bottom, wherein the bottom and the first side adjacent to the gate form an angled corner;
an epitaxial buffer layer lining the first side and bottom of the recess and includes a rounded corner over the angled corner; and
a stressor layer in the recess with the rounded corner.
2. The semiconductor device of claim 1 wherein the rounded corner is devoid of angles.
3. The semiconductor device of claim 1 wherein:
the stressor layer comprises an epitaxial stressor layer comprising Si and a component comprising Ge, Ar, Kr or Xe or a combination thereof.
4. The semiconductor device of claim 3 wherein:
the stressor layer comprises a graded concentration of the component, wherein the concentration of the component in a middle portion of the stressor layer is higher than at top and bottom portions.
5. The semiconductor device of claim 4 wherein:
the component comprises Ge; and
the concentration of Ge at the top portion is about 5-15 atomic percent and increases to about 10-40 atomic percent in the middle portion and decreases to about 0-20 atomic percent at the bottom portion.
6. The semiconductor device of claim 4 wherein the concentration of the component at a top portion is about 5-15 atomic percent and increases to about 10-40 atomic percent in the middle portion and decreases to about 0-20 atomic percent at a bottom portion.
7. The semiconductor device of claim 1 wherein:
the epitaxial buffer layer comprises undoped silicon, lightly doped silicon, SiC, SiGe or a combination thereof.
8. The semiconductor device of claim 1 wherein the stressor layer comprises a graded concentration of B dopants, wherein the concentration of B dopants at the top portion is about 1E20-2E21 atomscm3 and decreases to about 6E17-8E19 atomscm3 at the bottom portion.
9. A semiconductor device comprising:
a substrate having a gate;
first and second stressor regions in the substrate adjacent to the gate, wherein the stressor regions include recesses adjacent to the gate, wherein each of the recesses includes a first side adjacent to the gate, a second side opposing the first side and a bottom, wherein the bottom and the first side adjacent to the gate form an angled corner;
a buffer layer comprising an epitaxial material, the buffer layer lining the first sidewall and bottom of the recesses and includes a rounded corner over the angled corner; and
a stressor layer in the recesses with the rounded corner, wherein the stressor layer is doped with a dopant impurity.
10. The semiconductor device of claim 9 wherein the rounded corner is devoid of angles.
11. The semiconductor device of claim 9 wherein the buffer layer comprises undoped silicon, lightly doped silicon, SiC, SiGe or a combination thereof.
12. A semiconductor device comprising:
a substrate having a feature;
a recess in a region of the substrate adjacent to the feature, wherein the recess includes a first side adjacent to the feature, a second side opposing the first side and a bottom, wherein the bottom and the first side adjacent to the feature form an angled corner;
an epitaxial buffer layer lining the first side and the bottom of the recess and includes a rounded corner over the angled corner; and
a stressor layer in the recess with the rounded corner.
13. The semiconductor device of claim 12 wherein the rounded corner is devoid of angles.
14. The semiconductor device of claim 12 wherein the epitaxial buffer layer lines the whole first side and whole bottom of the recess.
15. The semiconductor device of claim 14 wherein the epitaxial buffer layer comprises undoped silicon, lightly doped silicon, SiC, SiGe or a combination thereof.
16. The semiconductor device of claim 12 wherein the stressor layer comprises an epitaxial stressor layer having a graded concentration of a component, wherein the concentration of the component in a middle portion of the stressor layer is higher than at top and bottom portions.
17. The semiconductor device of claim 16 wherein the stressor layer comprises an epitaxial layer comprising Si and the component comprising Ge, Ar, Kr or Xe or a combination thereof.
18. The semiconductor device of claim 17 wherein the concentration of Ge at the top portion is about 5-15 atomic percent and increases to about 10-40 atomic percent in the middle portion and decreases to about 0-20 atomic percent at the bottom portion.
19. The semiconductor device of claim 12 wherein the stressor layer comprises a graded concentration of B dopants, wherein the concentration of B dopants at the top portion is about 1E20-2E21 atomscm3 and decreases to about 6E17-8E19 atomscm3 at the bottom portion.
20. The semiconductor device of claim 12 wherein:
the epitaxial buffer layer comprises undoped silicon, lightly doped silicon, SiC, SiGe or a combination thereof.