1. An x86 architecture microprocessor having an x87 floating-point unit (FPU) with an x87 register stack, comprising:
an instruction decoder, configured to decode an x87 fused multiply-add (FMA) instruction of the microprocessor instruction set, wherein said FMA instruction implicitly specifies first and second operands as stored in first and second registers of the register stack, said first and second registers being the top two registers of the register stack, and a third operand, explicitly specified in the instruction as stored in a third register of the register stack;
a multiplier, coupled to the register stack, configured to multiply said first and second operands to generate a product, in response to said FMA instruction; and
an adder, coupled to said multiplier, configured to add said third operand to said product to generate a result, in response to said FMA instruction.
2. The microprocessor as recited in claim 1, wherein the microprocessor is further configured to store said result in said third register in said FPU register stack, in response to said FMA instruction.
3. The microprocessor as recited in claim 2, wherein the microprocessor is further configured to pop said first and second operands off the register stack, after storing said result into said third register of the register stack, in response to said FMA instruction.
4. The microprocessor as recited in claim 1, wherein the microprocessor is further configured to pop said first and second operands off the register stack, in response to said FMA instruction.
5. The microprocessor as recited in claim 1, wherein said FMA instruction further comprises:
an opcode, comprising one of the following hexadecimal values: 0xD9D4, 0xD9D5, 0xD9D6, 0xD9D7.
6. A method for executing an x87 fused multiply-add (FMA) instruction in an x86 architecture microprocessor having an x87 floating-point unit (FPU) with an x87 register stack, comprising:
decoding the FMA instruction of the microprocessor instruction set, wherein said FMA instruction having implicitly specifies first and second operands as stored in first and second registers of the register stack, said first and second registers being the top two registers of the register stack, and a third operand, explicitly specified in the instruction as stored in a third register of the register stack;
multiplying said first and second operands to generate a product, after said decoding; and
adding said third operand to said product to generate a result, after said multiplying.
7. The method as recited in claim 6, further comprising:
storing said result in said third register in said FPU register stack, after said adding.
8. The method as recited in claim 7, further comprising:
popping said first and second operands off the register stack, after said storing.
9. The method as recited in claim 6, further comprising:
popping said first and second operands off the register stack, after said adding.
10. The method as recited in claim 6, wherein said decoding comprises decoding an opcode of the FMA instruction, wherein said opcode comprises one of the following hexadecimal values: 0xD9D4, 0xD9D5, 0xD9D6, 0xD9D7.
11. A computer program product for use with a computing device, the computer program product comprising:
a computer usable storage medium, having computer readable program code embodied in said medium, for providing an x86 architecture microprocessor having an x87 floating-point unit (FPU) with an x87 register stack, said computer readable program code comprising:
first program code for providing an instruction decoder, configured to decode an x87 fused multiply-add (FMA) instruction of the microprocessor instruction set, wherein said FMA instruction implicitly specifies first and second operands as stored in first and second registers of the register stack, said first and second registers being the top two registers of the register stack, and a third operand, explicitly specified in the instruction as stored in a third register of the register stack;
second program code for providing a multiplier, coupled to the register stack, configured to multiply said first and second operands to generate a product, in response to said FMA instruction; and
third program code for providing an adder, coupled to said multiplier, configured to add said third operand to said product to generate a result, in response to said FMA instruction.
12. The computer program product as recited in claim 11, wherein the microprocessor is further configured to store said result in said third register in said FPU register stack, in response to said FMA instruction.
13. A method for providing an x86 architecture microprocessor having an x87 floating-point unit (FPU) with an x87 register stack, the method comprising:
providing computer-readable program code describing the microprocessor, the program code comprising:
first program code for providing an instruction decoder, configured to decode an x87 fused multiply-add (FMA) instruction of the microprocessor instruction set, wherein said FMA instruction implicitly specifies first and second operands as stored in first and second registers of the register stack, said first and second registers being the top two registers of the register stack, and a third operand, explicitly specified in the instruction as stored in a third register of the register stack;
second program code for providing a multiplier, coupled to the register stack, configured to multiply said first and second operands to generate a product, in response to said FMA instruction; and
third program code for providing an adder, coupled to said multiplier, configured to add said third operand to said product to generate a result, in response to said FMA instruction; and
transmitting the computer-readable program code as a computer data signal on a network.
14. The method as recited in claim 13, wherein the microprocessor is further configured to store said result in said third register in said FPU register stack, in response to said FMA instruction.
15. An x86 architecture microprocessor having an x87 floating-point unit (FPU) with an x87 register stack, comprising:
an instruction decoder, configured to decode an x87 fused multiply-add (FMA) instruction of the microprocessor instruction set, wherein said FMA instruction implicitly specifies first, second, and third operands as stored in first, second, and third registers of the register stack, said first, second, and third registers being the top three registers of the register stack;
a multiplier, coupled to the register stack, configured to multiply said first and second operands to generate a product, in response to said FMA instruction; and
an adder, coupled to said multiplier, configured to add said third operand to said product to generate a result for storing in said third register, in response to said FMA instruction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method of transmitting power control information to a BSC (Base Station Controller) in a BTS (Base station Transceiver System) of a mobile communication system, comprising the steps of:
receiving forward power control (FPC) mode information indicating a low power control from the BSC and transmitting the FPC mode information to an MS (Mobile Station);
extracting a QIB (Quality Indicator Bit) that is a power control command from a reverse pilot channel received from the MS according to the FPC mode information;
determining the status of the QIB; and
transmitting information requesting the BSC to change a threshold for a power control on a forward DCCH (Dedicated Control Channel) based on the determined QIB status to the BSC.
2. The method of claim 1, further comprising the steps of:
receiving FPC mode information indicating a fast power control from the BSC and transmitting the FPC mode information to the MS;
extracting a PCB (Power Control Bit) in every predetermined period from the reverse pilot channel received from the MS according to the FPC mode information; and
performing a fast forward power control according to the extracted PCB.
3. A method of transmitting power control information to a BSC in a BTS of a mobile communication system, comprising the steps of:
detecting a DTX (Discontinuous Transmission) period by measuring the energy of a DCCH frame received from an MS;
determining reception status by measuring the energy of a PCB on a reverse pilot channel if the DTX is detected;
determining FQI (Frame Quality Indicator) information according to the determined reception status; and
transmitting the FQI information to the BSC.
4. The method of claim 3, wherein the step of determining reception status comprises the steps of:
comparing the measured energy with a predetermined threshold;
determining that the reception status is good if the energy is greater than the threshold; and
determining that the reception status is bad if the energy is less than the threshold.
5. The method of claim 3, wherein the step of determining reception status comprises the steps of:
determining an FER (Frame Error Rate) corresponding to the measured energy;
generating a random number in a predetermined range;
determining that the reception status is good if the random number is greater than the FER; and
determining that the reception status is bad if the random number is less than the FER.
6. A method of transmitting power control information to a BTS in a BSC of a mobile communication system, comprising the steps of:
checking FQI information in the latest reverse DCCH message received from the BSC if the frame content of the reverse message indicates a null frame;
determining a reverse link power control threshold based on the FQI information; and
transmitting a forward DCCH message with the threshold to the BTS.
7. The method of claim 6, further comprising the step of setting power control information requesting the MS to increase transmission power in the forward DCCH message and transmitting the forward DCCH message to the BTS if the frame content of the reverse message indicates an erasure frame.
8. The method of claim 6, further comprising the step of setting the power control information of the reverse message in the forward DCCH message and transmitting the forward DCCH message to the BTS if the frame content of the reverse message indicates a data frame.
9. The method of claim 6, further comprising the step of setting an initial value for the reverse link power control in the forward DCCH message and transmitting the forward DCCH message to the BTS if the frame content of the reverse message indicates an idle frame.
10. The method of claim 6, further comprising the step of setting information for a slow forward power control in the forward DCCH message and transmitting the forward DCCH message to the BTS if the frame content of the forward DCCH message indicates a null frame.
11. A method of transmitting power control information to a BTS in a BSC of a mobile communication system, comprising the steps of:
receiving a reverse DCCH message from the BTS;
extracting QIB information from the reverse DCCH message;
determining a threshold for a slow forward power control based on the QIB information; and
transmitting a forward DCCH message including the slow forward power control threshold to the BTS.
12. A method of transmitting power control information to a BSC in a BTS of a mobile communication system, comprising the steps of:
receiving FPC mode information indicating a slow power control from the BSC and transmitting the FPC mode information to an MS; and
extracting a QIB that is a power control command in a frame period from a reverse pilot channel received from the MS according to the FPC mode information and transmitting the QIB to the BSC.
13. The method of claim 12, further comprising the step of receiving a threshold for a forward power control that is determined based on the QIB from the BSC.
14. A method of transmitting power control information to a BSC in a BTS of a mobile communication system, comprising the steps of:
extracting power control information from a radio frame received from an MS according to a set FPC mode;
performing a fast power control if the extracted power control information is a PCB and resetting a predetermined first field in a reverse DCCH message;
performing a slow power control if the extracted power control information is a QIB and setting the first field to a QIB status value in the reverse DCCH message;
setting a predetermined second field in the reverse DCCH message according to the energy measurement of the extracted power control information; and
transmitting the reverse DCCH message to the BSC.
15. The method of claim 14, wherein the second field is FQI (Frame Quality Indicator) information.