1. A controller comprising:
an instruction table memory in which an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory is stored;
a program counter to which a read address in the instruction table memory to access the nonvolatile semiconductor memory is set;
a first decoder which decodes the instruction code read from the instruction table memory to output a first decode signal; and
a first executing unit which executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.
2. The controller according to claim 1, further comprising:
a command latch circuit in which a command externally input is stored; and
a CPU which decodes the command stored in the command latch circuit and sets the read address in the instruction table memory to the program counter on the basis of a result decoded by the CPU.
3. The controller according to claim 2,
wherein, when the nonvolatile semiconductor memory is continuously accessed, the address set to the program counter is incremented.
4. The controller according to claim 1,
wherein the instruction table memory stores an instruction code to continuously access the instruction codes in an arbitrary order.
5. The controller according to claim 1, further comprising:
a second decoder which decodes a command externally input to output a second decode signal; and
a second executing unit which sets the read address to the program counter on the basis of the second decode signal output from the second decoder.
6. The controller according to claim 5,
wherein a dedicated line to set the read address to the program counter is arranged between the second executing unit and the program counter.
7. The controller according to claim 5, further comprising:
a command latch circuit in which the command externally input is stored,
wherein the command stored in the command latch circuit is decoded by the second decoder.
8. The controller according to claim 5,
wherein when the nonvolatile semiconductor memory is continuously accessed, the address set to the program counter is incremented.
9. The controller according to claim 5,
wherein the instruction table memory stores an instruction code to continuously access the instruction codes in an arbitrary order.
10. A controller comprising:
a register in which information to access a nonvolatile semiconductor memory is stored;
a decoder which decodes a command externally input to output a decode signal;
an executing unit which sets the information to access the nonvolatile semiconductor memory to the register on the basis of the decode signal output from the decoder; and
an inputoutput control circuit which accesses the nonvolatile semiconductor memory according to the information stored in the register.
11. The controller according to claim 10,
wherein a dedicated line to set the information to the register is arranged between the executing unit and the register.
12. The controller according to claim 10, further comprising:
a command latch circuit in which the command externally input is stored,
wherein the command stored in the command latch circuit is decoded by the decoder.
13. The controller according to claim 10,
wherein when the nonvolatile semiconductor memory is continuously accessed, the executing unit sets information to access the nonvolatile semiconductor memory to the register.
14. The controller according to claim 10,
wherein the instruction table memory stores an instruction code to continuously access the instruction codes in an arbitrary order.
15. A semiconductor memory device comprising:
a nonvolatile semiconductor memory in which data can be electrically rewritten; and
a controller which controls an operation of the nonvolatile semiconductor memory,
wherein the controller includes:
an instruction table memory in which an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory is stored;
a program counter to which a read address in the instruction table memory to access the nonvolatile semiconductor memory is set;
a decoder which decodes the instruction code read from the instruction table memory to output a decode signal; and
an executing unit which executes access to the nonvolatile semiconductor memory on the basis of the decode signal output from the decoder.
16. The semiconductor memory device according to claim 15, further comprising:
a command latch circuit in which a command externally input is stored; and
a CPU which decodes the command stored in the command latch circuit and sets the read address in the instruction table memory to the program counter on the basis of a result decoded by the CPU.
17. The semiconductor memory device according to claim 16,
wherein when the nonvolatile semiconductor memory is continuously accessed, the address set to the program counter is incremented.
18. The controller according to claim 15,
wherein the instruction table memory stores an instruction code to continuously access the instruction codes in an arbitrary order.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer-implemented method for scheduling a process flow segment to be performed within a computer system based on user behavior, comprising:
designating at least one available user input selection in the first process flow as being associated with the process flow segment, the first process flow comprising a plurality of process flow tasks;
receiving input from a user selecting at least one of the designated available user input selections, and storing first information associated with that received input in a data set;
analyzing the data set to determine whether local criteria associated with the process flow segment has been satisfied; and
if the local criteria associated with the process flow segment has been satisfied, scheduling the process flow segment to be performed, wherein the process flow segment is scheduled to be performed contemporaneously with process flow tasks from the first process flow.
2. The computer-implemented method of claim 1, wherein the content of the stored first information associated with the received input includes at least one selected from the group including, the date the input occurred, the particular user associated with the input, and an event identifier associated with the selected one of the at least one of the designated available user input selections.
3. The computer-implemented method of claim 1, wherein the scheduling of the process flow segment to be performed causes the process flow segment to be performed within the first process flow.
4. The computer-implemented method of claim 1, wherein the scheduling of the process flow segment to be performed causes the process flow segment to be performed contemporaneously with a second process flow.
5. The computer-implemented method of claim 1, wherein the process flow segment includes a plurality of process flow events.
6. The computer-implemented method of claim 1, wherein the content of the stored first information is at least partly derived from the criteria associated with the process flow segment.
7. The computer-implemented method of claim 1, wherein the process flow segment includes at least one process flow event which causes second information to be displayed on a display device.
8. The computer-implemented method of claim 1, wherein the data set includes data from a present user session of the user and data from at least one previous user session of the user.
9. The computer-implemented method of claim 1, further including
analyzing the data set to determine whether global criteria has been satisfied; and
wherein the scheduling of the process flow segment to be performed occurs only if the global criteria and the local criteria have both been satisfied.
10. The computer-implemented method of claim 1, wherein the criteria associated with the process flow segment has a plurality of aspects that must be satisfied in order for scheduling to occur.
11. The computer-implemented method of claim 1, wherein the criteria associated with the process flow segment, and the process flow segment composition are both predetermined and static.
12. The computer-implemented method of claim 1, wherein at least one of the criteria associated with the process flow segment and the process flow segment composition is determined at least partly by comparing at least a portion of the data set with aggregated information.
13. A non-transitory computer-readable storage medium storing instructions that when executed by a computing device cause the computing device to perform a method for scheduling a process flow segment to be performed within the computing device based on user behavior, the method comprising:
designating at least one available user input selection in the first process flow as being associated with the process flow segment, the first process flow comprising a plurality of process flow tasks;
receiving input from a user selecting at least one of the designated available user input selections, and storing first information associated with that received input in a data set;
analyzing the data set to determine whether local criteria associated with the process flow segment has been satisfied; and
scheduling, if the local criteria associated with the process flow segment has been satisfied, the process flow segment to be performed, wherein the process flow segment is scheduled to be performed contemporaneously with process flow tasks from the first process flow.