1. A semiconductor memory device comprising:
a plurality of memory cell arrays having a plurality of memory cells or memory cell units each of which include a plurality of memory cells, arranged in a matrix, the plurality of memory cell arrays being located independently of each other;
a first memory cell array included in the plurality of memory cell arrays;
a second memory cell array included in the plurality of memory cell arrays;
a third memory cell array included in the plurality of memory cell arrays;
a fourth memory cell array included in the plurality of memory cell arrays;
a first memory cell array group including the first memory cell array and the second memory cell array; and
a second memory cell array group including the third memory cell array and the fourth memory cell array,
wherein the first memory cell array, the second memory cell array, the third memory cell array and the fourth memory cell array are different from one another, a first PassFail signal indicative of success or failure of an operation is outputted in accordance with each of the first memory cell array group and the second memory cell array group.
2. The semiconductor memory device according to claim 1, wherein the operation includes a parallel operation with respect to both of memory cells in the first memory cell array group and memory cells in the second memory cell array group.
3. The semiconductor memory device according to claim 1, wherein the operation includes a parallel operation with respect to memory cells in two or more of the plurality of memory cell arrays.
4. The semiconductor memory device according to claim 1, wherein the operation is a program or erase operation.
5. The semiconductor memory device according to claim 1, wherein the first PassFail signal is a PassFail signal indicating whether the operation has attained success with respect to all of selected memory cells included in each of the first memory cell array group and the second memory cell array group or not.
6. The semiconductor memory device according to claim 1, wherein a second PassFail signal of an entire chip is also outputted when the first PassFail signal is outputted.
7. The semiconductor memory device according to claim 1, wherein the first PassFail signal is a PassFail signal indicating whether the operation has attained success with respect to one memory cell array selected from the two or more memory cell arrays in each of the first memory cell array group and the second memory cell array group or not.
8. The semiconductor memory device according to claim 1, wherein the first PassFail signal is outputted after a first command is inputted.
9. The semiconductor memory device according to claim 8, wherein the first PassFail signal is not outputted and a third PassFail signal which is different from the first PassFail signal is outputted after a second command is inputted.
10. The semiconductor memory device according to claim 8, wherein a fourth PassFail signal is outputted with respect to each of the memory cell arrays included in an entire chip after a third command is input.
11. The semiconductor memory device according to claim 10, wherein the third command is different from the first command.
12. The semiconductor memory device according to claim 1,
wherein the memory cell is EEPROM.
13. The semiconductor memory device according to claim 1, wherein the memory cell unit is a NAND cell type EEPROM.
14. A semiconductor memory device comprising:
a plurality of memory cell arrays having a plurality of memory cells or memory cell units each of which includes a plurality of memory cells, arranged in a matrix, the plurality of memory cell arrays being located independently of each other;
a first memory cell array included in the plurality of memory cell arrays;
a second memory cell array included in the plurality of memory cell arrays;
a third memory cell array included in the plurality of memory cell arrays;
a fourth memory cell array included in the plurality of memory cell arrays;
a first memory cell array group including the first memory cell array and the second memory cell array; and
a second memory cell array group including the third memory cell array and the fourth memory cell array,
wherein the first memory cell array, the second memory cell array, the third memory cell array and the fourth memory cell array are different from one another, and first PassFail signals, each of which indicates success or failure of an operation of a respective one of the first memory cell array group and the second memory cell array group, are outputted.
15. The semiconductor memory device according to claim 14, wherein the operation includes a parallel operation with respect to both of memory cells in the first memory cell array group and memory cells in the second memory cell array group.
16. The semiconductor memory device according to claim 14, wherein the operation includes a parallel operation with respect to memory cells in two or more of the plurality of memory cell arrays.
17. The semiconductor memory device according to claim 14, wherein the operation is a program or erase operation.
18. The semiconductor memory device according to claim 14, wherein the first PassFail signal is a PassFail signal indicating whether the operation has attained success with respect to all of selected memory cells included in each of the first memory cell array group and the second memory cell array group or not.
19. The semiconductor memory device according to claim 14, wherein a second PassFail signal of an entire chip is also outputted when the first PassFail signal is outputted.
20. The semiconductor memory device according to claim 14, wherein the first PassFail signal is a PassFail signal indicating whether the operation has attained success with respect to one memory cell array selected from the two or more memory cell arrays in each of the first memory cell array group and the second memory cell array group.
21. The semiconductor memory device according to claim 14, wherein the memory cell unit is a NAND cell type EEPROM.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A scope mount to be removeably mounted on a plurality of rifles comprising:
a pair of mounting bases comprising a front and a rear mounting base for attachment to a rifle;
a pair of mounting rings comprising a front and a rear mounting ring for attachment of a scope to said mounting bases.
2. A scope mount as in claim 1, wherein each of said mounting bases comprise a rectangular element having a first top surface, a second bottom surface, and two identical side surfaces.
3. The scope mount of claim 2, wherein said first top surface comprises a planar surface, and said second bottom surface comprises a planar surface and a shallow radius running the length of said second bottom surface of said mounting bases, for attachment to either round or planar surfaces of a rifle.
4. A scope mount as in claim 2, wherein each of said front and rear mounting bases each further comprise two opposed longitudinal channels along said side surfaces, for receiving said front and rear mounting rings.
5. The scope mount of claim 4, wherein said front and rear mounting bases each comprise a plurality of vertical mounting holes through said front and rear mounting bases, through which mounting screws in combinations of two per front mounting base and two per rear mounting base, removeably attach said front mounting base and said rear mounting base to a plurality of rifles, having a plurality of corresponding mounting patterns thereupon.
6. A scope mount as in claim 5, wherein both said front and rear mounting bases each comprise a pair of horizontal attachment holes interspaced between said vertical mounting holes, for receiving mounting screws attaching said front and rear scope rings to said front and rear mounting bases respectively.
7. A scope mount to be removeably mounted on a plurality of rifles comprising:
a pair of mounting bases comprising a front and a rear mounting base for attachment to a rifle;
a pair of mounting rings comprising a front and a rear mounting ring for attachment of a scope to said mounting bases, wherein said front and rear mounting rings comprise:
an upper scope ring for receiving the body of a scope and;
a pair of opposing bowed-in mounting leg members extending downward for attachment to said front and rear mounting bases.
8. The front and rear mounting rings of claim 7, wherein said leg members comprise inward, opposing flanges, to be received within opposed longitudinal channels along said side surfaces of said front and rear mounting bases.
9. The front and read mounting rings of claim 8 wherein said leg members comprise at least one pair of opposing congruent holes though said leg members and said flanges, wherein at least one of said congruent holes is threaded for receiving a machine screw fed through said opposing hole
10. The front and rear mounting rings of claim 7 wherein said upper scope ring comprises:
a lower, semi-circular mounting portion and;
a corresponding upper semi-circular attachment element.
11. The front and rear mounting rings of claim 10, wherein said lower semi-circular mounting portion of said upper scope ring has two horizontal flanges corresponding to congruent horizontal flanges on said upper semi-circular circular attachment elements, for removeably receiving a body of a scope there between.
12. The front and rear mounting rings of claim 11, wherein said horizontal flanges of said lower mounting portion and said horizontal flanges of said upper attachment element comprise a plurality of opposing, congruent holes there through, wherein at least one of said congruent holes is threaded for receiving a machine screw fed through said opposing hole.