1. A storage device capable of retaining data in a stand-by mode, said storage device comprises:
one or more storage array nodes;
a Rail to Rail voltage adjustor configured to selectively alter the voltage provided at each said storage array node during the stand-by mode;
a storage array operatively coupled to said Rail to Rail voltage adjustor; and
a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during the stand-by mode.
2. A storage device as claimed in claim 1 wherein said storage array comprises an array of memory cell rows and columns operable in a stand-by mode.
3. A storage device as claimed in claim 1, wherein said Rail to Rail voltage adjustor comprises at least one switched voltage-reduction element.
4. A storage device as claimed in claim 1 wherein said Rail to Rail voltage monitor comprises a low leakage tracking block producing at least one control signal depending on the supply voltage.
5. A storage device as claimed in claim 4 wherein said low leakage tracking block comprises:
a reference column comprising an array of memory cell rows and columns greater than memory cell rows and columns in the storage array; and
a level sensing block comprising non inverting buffer.
6. A system capable of retaining data in a stand-by mode, said system comprises:
one or more storage array nodes;
a Rail to Rail voltage adjustor configured to selectively alter the voltage provided at each said storage array node during the stand-by mode;
a storage array operatively coupled to said Rail to Rail voltage adjustor; and
a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during the stand-by mode.
7. A system as claimed in claim 6 wherein said storage array comprises an array of memory cell rows and columns operable in a stand-by mode.
8. A system as claimed in claim 6, wherein said Rail to Rail voltage adjustor comprises at least one switched voltage-reduction element.
9. A system as claimed in claim 6 wherein said Rail to Rail voltage monitor comprises a low leakage tracking block producing at least one control signal depending on the supply voltage nodes.
10. A system as claimed in claim 9 wherein said low leakage tracking block comprises:
a reference column comprising an array of memory cell rows and columns greater than memory cell rows and columns in the storage array; and
a level sensing block comprising non inverting buffer.
11. A method for retention of data in a storage device during standby mode comprising:
monitoring each supply voltage node operatively coupled to said storage array;
monitoring Rail to Rail voltage at each storage array node of said storage array;
determining an operating band of Rail to Rail voltage; and
selectively altering voltage provided at each said storage array node during the stand-by mode.
12. A method as claimed in claim 11 wherein selectively altering the voltage provided at each storage array node comprises:
applying no sleep to the storage device when the Rail to Rail voltage falls within an operating band of low voltages;
applying sleep either to header or footer of the storage device when the Rail to Rail voltage falls within an operating band of intermediate voltages; and
applying full sleep to the storage device when the Rail to Rail voltage falls within an operating band of high voltages.
13. A power controller, comprising:
a first input supply node operable to receive a first input supply signal;
a first output supply node operable to provide a first output supply signal;
a monitor operable to monitor the first input supply signal; and
an adjuster operable to adjust the first output supply signal in response to the monitor.
14. The power controller of claim 13 wherein the monitor is operable to determine a level of the first input supply signal at the first input supply node relative to at least one reference signal level.
15. The power controller of claim 13 wherein:
the monitor comprises:
a column of memory cells coupled to the first input supply node; and
a comparator coupled to the column and operable to generate a comparison signal; and
the adjuster is operable to adjust the first output supply signal in response to the comparison signal.
16. The power controller of claim 13 wherein:
the monitor comprises:
a column of memory cells coupled to the first input supply node; and
a Schmidt trigger coupled to the column and operable to generate a trigger signal; and
the adjuster is operable to adjust the first output supply signal in response to the trigger signal.
17. The power controller of claim 13 wherein the adjuster is operable to adjust an impedance between the first input and output supply nodes in response to the monitor.
18. The power controller of claim 13 wherein the adjuster comprises a transistor having a conduction path coupled between the first input and first output supply nodes and having a control node coupled to the monitor.
19. The power controller of claim 13 wherein:
the first input supply signal comprises a first input supply voltage; and
the first output supply signal comprises a first output supply voltage.
20. The power controller of claim 13, further comprising:
a second input supply node operable to receive a second input supply signal;
a second output supply node operable to provide a second output supply signal; and
wherein the adjuster is operable to adjust the second output supply signal in response to the monitor.
21. The power controller of claim 20 wherein:
the monitor comprises:
a column of memory cells coupled to the first and second input supply nodes; and
a comparator coupled to the column and operable to generate a comparison signal; and
the adjuster is operable to adjust the first and second output supply signals in response to the comparison signal.
22. The power controller of claim 20 wherein:
the monitor comprises:
a column of memory cells coupled to the first and second input supply nodes; and
a Schmidt trigger coupled to the column and operable to generate a trigger signal; and
the adjuster is operable to adjust the first and second output supply signals in response to the trigger signal.
23. The power controller of claim 20 wherein the adjuster is operable to adjust a first impedance between the first input and output supply nodes and a second impedance between the second input and output supply nodes in response to the monitor.
24. The power controller of claim 20 wherein the adjuster comprises:
a first transistor having a conduction path coupled between the first input and first output supply nodes and having a control node coupled to the monitor; and
a second transistor having a conduction path coupled between the second input and second output supply nodes and having a control node coupled to the monitor.
25. The power controller of claim 24 wherein:
the monitor is operable to determine whether the first input supply signal is less than a first reference value, between the first and a second reference value, or greater than the second reference value; and
the adjuster is operable to activate the first and second transistors while the first input supply signal is less than the first reference value, to activate only one of the first and second transistors while the first input supply signal is between the first and second reference values, and to deactivate the first and second transistors while the first input supply signal is greater than the second reference value.
26. The power controller of claim 24 wherein:
the monitor is operable to determine whether the first input supply signal is between first and second reference values, between the second and a third reference value, or greater than the third reference value; and
the adjuster is operable to activate the first and second transistors while the first input supply signal is between the first and second reference values, to activate only one of the first and second transistors while the first input supply signal is between the second and third reference values, and to deactivate the first and second transistors while the first input supply signal is greater than the third reference value.
27. The power controller of claim 20 wherein:
the first and second input supply signals respectively comprise first and second input supply voltages; and
the first and second output supply signals respectively comprise first and second output supply voltages.
28. An integrated circuit, comprising:
a first input supply node operable to receive a first input supply signal;
a first output supply node operable to provide a first output supply signal;
a monitor operable to monitor the first input supply signal;
an adjuster operable to adjust the first output supply signal in response to the monitor; and
an array of circuit elements having a first array supply node coupled to the first output supply node.
29. The integrated circuit of claim 28, further comprising:
a second input supply node operable to receive a second input supply signal;
a second output supply node operable to provide a second output supply signal;
wherein the adjuster is operable to adjust the second output supply signal in response to the monitor; and
wherein the array has a second array supply node coupled to the second output supply node.
30. The integrated circuits of claim 28 wherein at least some of the circuit elements of the array comprise memory cells.
31. A system, comprising:
a first integrated circuit, comprising:
a first input supply node operable to receive a first input supply signal;
a first output supply node operable to provide a first output supply signal;
a monitor operable to monitor the first input supply signal;
an adjuster operable to adjust the first output supply signal in response to the monitor; and
an array of circuit elements having a first array supply node coupled to the first output supply node; and
a second integrated circuit coupled to the first integrated circuit.
32. The system of claim 31 wherein the second integrated circuit comprises a controller.
33. The system of claim 31 wherein the first and second integrated circuits are disposed on a same integrated-circuit die.
34. The system of claim 31 wherein the first and second integrated circuits are disposed on respective integrated-circuit dies.
35. A method, comprising:
monitoring a first input supply signal; and
varying a first output supply signal in response to the first input supply signal.
36. The method of claim 35 wherein:
monitoring comprises monitoring a level of the first input supply signal; and
varying comprises varying a level of the first output supply signal in response to the level of the first input supply signal.
37. The method of claim 35, further comprising generating the first output supply signal from the first input supply signal.
38. The method of claim 35 wherein varying comprises varying an impedance disposed between the first and second input supply signals.
39. The method of claim 35 wherein:
monitoring comprises determining whether the first input supply signal is less than a first reference value;
varying the first output supply signal comprises causing an impedance between the first input and output supply signals to have a lower value if the first input supply signal is less than the first reference value, and to have a higher value if the first input supply signal is greater than the first reference value.
40. The method of claim 35, further comprising:
wherein monitoring comprises determining whether the first input supply signal is less than a first reference value, between the first and a second reference value, or greater than the second reference value;
wherein varying the first output supply signal comprises causing a first impedance between the first input and output supply signals to have a first lower value if the first input supply signal is less than the first reference value, to have one of the first lower and a first higher value if the first input supply signal is between the first and second reference values, and to have the first higher value if the first input supply signal is greater than the second reference value; and
varying a second output supply signal by causing a second impedance between a second input supply signal and the second output supply signal to have a second lower value if the first input supply signal is less than the first reference value, to have one of the second lower and a second higher value if the first input supply signal is between the first and second reference values, and to have the second higher value if the first input supply signal is greater than the second reference value.
41. The method of claim 35, further comprising:
wherein monitoring comprises determining whether the first input supply signal is between a first reference value and a second reference value, between the second and a third reference value, or greater than the third reference value;
wherein varying the first output supply signal comprises causing a first impedance between the first input and output supply signals to have a first lower value if the first input supply signal is between the first and second reference values, to have one of the first lower and a first higher value if the first input supply signal is between the second and third reference values, and to have the first higher value if the first input supply signal is greater than the third reference value; and
varying a second output supply signal by causing a second impedance between a second input supply signal and the second output supply signal to have a second lower value if the first input supply signal is between the first and second reference values, to have one of the second lower and a second higher value if the first input supply signal is between the second and third reference values, and to have the second higher value if the first input supply signal is greater than the third reference value.
42. The method of claim 35 wherein:
monitoring comprises determining whether the first input supply signal is less than a first reference value; and
varying the first output supply signal comprises causing the first output supply signal to have a substantially constant level regardless of whether the first input supply signal is less than or greater than the first reference value.
43. The method of claim 35 wherein:
monitoring comprises determining whether the first input supply signal is less than a first reference value, between the first and a second reference value, or greater than the second reference value; and
varying the first output supply signal comprises causing the first output supply signal to have a substantially constant level regardless of whether the first input supply signal is less than the first reference value, between the first and second reference values, or greater than the second reference value.
44. The method of claim 35 wherein:
monitoring comprises determining whether the first input supply signal is between first and second reference values, between the second and a third reference value, or greater than the third reference value; and
varying the first output supply signal comprises causing the first output supply signal to have a substantially constant level regardless of whether the first input supply signal is between the first and second reference values, between the second and third reference values, or greater than the third reference value.
45. The method of claim 35 wherein:
monitoring comprises determining whether the first input supply signal is less than a first reference value;
varying the first output supply signal comprises causing the first output supply signal to have a level within a range regardless of whether the first input supply signal is less than or greater than the first reference value, the range causing a memory array coupled to the first output supply signal to retain its contents and to have a leakage current that is less than a threshold.
46. The method of claim 35, further comprising:
wherein monitoring comprises determining whether the first input supply signal is less than a first reference value, between the first and a second reference value, or greater than the second reference value;
varying the first output supply signal comprises causing the first output supply signal to have a level within a range regardless of whether the first input supply signal is less than the first reference value, between the first and second reference values, or greater than the second reference value, the range causing a memory array coupled to the first output supply signal to retain its contents and to have a leakage current that is less than a threshold.
47. The method of claim 35, further comprising:
wherein monitoring comprises determining whether the first input supply signal is between first and second reference values, between the second and a third reference values, or greater than the third reference value;
varying the first output supply signal comprises causing the first output supply signal to have a level within a range regardless of whether the first input supply signal is between the first and second reference values, between the second and third reference values, or greater than the third reference value, the range causing a memory array coupled to the first output supply signal to retain its contents and to have a leakage current that is less than a threshold.
48. The method of claim 35, further comprising:
wherein monitoring comprises determining whether the first input supply signal is less than a first reference value, between the first and a second reference value, or greater than the second reference value;
varying the first output supply signal comprises causing the first output supply signal to have a level within a first range regardless of whether the first input supply signal is less than the first reference value, between the first and second reference values, or greater than the second reference value;
varying a second output supply signal by causing the second output supply signal have a level within a second range regardless of whether the first input supply signal is less than the first reference value, between the first and second reference values, or greater than the second reference value; and
wherein the first and second ranges cause a memory array coupled to the first and second output supply signals to retain its contents and to have a leakage current that is less than a threshold.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-18. (canceled)
19. A method of using an analyte meter, comprising:
contacting a sample fluid with a sensor positioned in an analyte meter, wherein the sensor comprises:
a first pair of electrodes;
a second pair of electrodes;
a sample chamber for holding the sample fluid, the sample chamber comprising the first pair of electrodes and the second pair of electrodes; and
an analyte-responsive enzyme and a redox mediator disposed in the sample chamber;
applying a potential between the first pair of electrodes using the analyte meter and detecting a change in an electrical signal between the first pair of electrodes to determine when the sample fluid contacts the first pair of electrodes;
applying a potential between the second pair of electrodes using the analyte meter and determining whether a change in an electrical signal occurs between the second pair of electrodes to determine whether the sample fluid contacts the second pair of electrodes; and
preventing an analyte concentration determining assay from running when a change in an electrical signal does not occur between the second pair of electrodes.
20. The method according to claim 19, wherein detecting a change in an electrical signal between the first pair of electrodes comprises detecting a voltage, current, resistance, impedance, capacitance, or combination thereof between the first pair of electrodes.
21. The method according to claim 20, wherein detecting a change in an electrical signal between the first pair of electrodes comprises detecting the production of a current between the first pair of electrodes.
22. The method according to claim 19, wherein determining whether a change in an electrical signal occurs between the second pair of electrodes comprises determining whether a voltage, current, resistance, impedance, capacitance, or combination thereof occurs between the second pair of electrodes.
23. The method according to claim 22, wherein determining whether a change in an electrical signal occurs between the second pair of electrodes comprises determining whether a current is produced between the second pair of electrodes.
24. The method according to claim 19, wherein the first pair of electrodes and second pair of electrodes are coplanar.
25. The method according to claim 19, wherein the sensor is a tip-fill sensor.
26. The method according to claim 19, wherein the sensor is a side-fill sensor.
27. The method according to claim 19, wherein the sample chamber is sized to contain a volume of no more than 1 \u03bcL of the sample fluid.
28. The method according to claim 27, wherein the sample chamber is sized to contain a volume of no more than 0.5 \u03bcL of the sample fluid.
29. The method according to claim 19, wherein the analyte is glucose.
30. The method according to claim 29, wherein the analyte-responsive enzyme is glucose oxidase or glucose dehydrogenase.
31. The method according to claim 19, wherein the analyte is a ketone.
32. The method according to claim 19, wherein the sample fluid is a blood sample, and wherein the method further comprises obtaining the blood sample from a finger of a subject.
33. The method according to claim 19, wherein the sample fluid is a blood sample, and wherein the method further comprises obtaining the blood sample from a region of a subject having a lower nerve end density as compared to a fingertip.
34. The method according to claim 33, wherein the region of a subject having a lower nerve end density as compared to a fingertip is selected from the group consisting of: a forearm region, and a thigh region.