1. A method of fabricating an isolated transistor comprising:
providing a semiconductor substrate having a device structure thereon, the device structure comprising a channel structure and a control electrode structure overlying the channel structure, the channel structure being suspended over the semiconductor substrate and underlying the control electrode structure;
depositing a channel isolation layer between the channel structure and the semiconductor substrate;
forming a current electrode dielectric isolation structure laterally disposed to the channel structure; and
depositing a current electrode structure over the current electrode dielectric isolation structure.
2. The method of claim 1 wherein the providing the semiconductor substrate and device structure comprises:
providing the semiconductor substrate;
forming a first layer of a first composition;
forming a second layer of a second composition over the first layer, the second layer for providing the channel structure;
forming a dielectric layer over the second layer; and
forming at least a portion of the control electrode structure over the dielectric layer.
3. The method of claim 2 wherein the providing the semiconductor substrate and device structure further comprises:
etching the dielectric layer and the first and second layers over a plurality of current electrode regions disposed laterally from the control electrode structure; and
etching the first layer to substantially remove the first layer from under the second layer to provide a void underlying a channel region of the device structure.
4. The method of claim 2 wherein:
forming the first layer of the first composition comprises forming silicon germanium;
forming the second layer of the second composition comprises forming silicon; and
forming the dielectric layer comprises forming silicon dioxide.
5. The method of claim 1 wherein the depositing the channel isolation layer comprises using at least one technique from the group consisting of chemical vapor deposition and plasma vapor deposition.
6. The method of claim 1 wherein the channel isolation layer comprises three sublayers, and the depositing the channel isolation layer comprises:
forming a first dielectric layer substantially around the device structure, and a second dielectric layer over the semiconductor substrate and under the channel structure, the first and second dielectric layers having a first etch characteristic; and
forming a third dielectric layer substantially around the first dielectric layer and over the second dielectric layer under the channel structure, the third dielectric layer having a second etch characteristic.
7. The method of claim 6 further comprising:
removing at least a portion of the third dielectric layer to expose a top surface of the semiconductor substrate.
8. The method of claim 7 wherein the removing comprises anisotropically etching the third dielectric layer to selectively and substantially remove the third dielectric layer from over the device structure.
9. The method of claim 7 further comprising:
forming a recess in the semiconductor substrate.
10. The method of claim 6 wherein:
forming the first and second dielectric layers comprises forming an oxide; and
forming the third dielectric layer comprise forming a nitride.
11. The method of claim 1 wherein the forming the current electrode dielectric isolation structure comprises:
subjecting the semiconductor substrate to an oxygen containing environment; and
oxidizing a top surface of the semiconductor substrate at least at the current electrode structure to grow an oxide isolation structure over the semiconductor substrate, the current electrode dielectric isolation structure comprising the oxide isolation structure.
12. The method of claim 11 wherein the semiconductor substrate is subjected to the oxygen containing environment through at least a portion of a dielectric layer disposed over the semiconductor substrate.
13. The method of claim 1 wherein the current electrode dielectric isolation structure is formed within the semiconductor substrate.
14. The method of claim 1 wherein the depositing current electrode structures over the current electrode structures comprises growing the current electrode structures using selective epitaxy.
15. A method of fabricating a semiconductor device, the method comprising:
forming a first dielectric isolation structure within a semiconductor substrate;
forming a second dielectric isolation structure within the semiconductor substrate;
forming a third dielectric isolation structure abutting the first and second dielectric isolation structures and between the semiconductor substrate and a crystalline structure suspended over the semiconductor substrate by a supporting structure coupled to the semiconductor substrate;
depositing a first current electrode structure over the first dielectric isolation structure; and
depositing a second current electrode structure over the second dielectric isolation structure.
16. The method of claim 15 wherein: forming the first semiconductor process and forming the second dielectric isolation structure are performed simultaneously.
17. The method of claim 15 wherein the forming the third dielectric isolation structure is performed at a different time than the forming the first dielectric isolation structure and the forming the second dielectric isolation structure.
18. The method of claim 15 wherein the forming the first dielectric isolation structure and forming the second dielectric isolation structure are performed at substantially the same time.
19. The method of claim 18 wherein the depositing the first current electrode structure and depositing the second current electrode structure are performed at substantially the same time.
20. The method of claim 15 wherein the depositing the first current electrode structure and depositing the second current electrode structure are performed at substantially the same time.
21. A method of fabricating an isolated transistor comprising:
providing a substrate;
forming a channel isolation structure underlying a channel structure;
forming a current electrode isolation structure in the substrate at each one of first and second current electrode regions disposed laterally to the channel structure, the channel isolation structure and the current electrode isolation structures being formed to adjoin; and
epitaxially growing a current electrode over each of the current electrode isolation structures.
22. The method of claim 21 wherein the forming the current electrode isolation structures comprises oxidizing at least a portion of the substrate.
23. The method of claim 21 wherein the channel isolation structure comprises a plurality of dielectric layers, the forming the channel isolation structure comprising:
forming a first dielectric layer under the channel structure;
forming a second dielectric layer on the semiconductor substrate; and
forming a third dielectric layer between the first and second dielectric layers.
24. The method of claim 23 wherein the forming the first dielectric layer and forming the second dielectric layer on the substrate are performed at substantially the same time.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for parallel computation of a Hough transform, the system comprising:
a plurality of processors capable of parallel operation;
a first memory interface for retrieving a data value from an image memory and
passing the data value to each of the plurality of processors; and
a plurality of Hough transform sub-space memories, each associated with a
processor of the plurality of processors;
wherein a processor of the plurality of processors is operable to receive the data value from the first memory interface and update Hough transform values in the associated memory of the plurality of Hough transform sub-space memories.
2. A system in accordance with claim 1, further comprising an image memory operable to store a plurality of data values.
3. A system in accordance with claim 2, further comprising a pre-processor, operable to pre-process a plurality of pixel values of an image to produce the plurality of data values in the image memory.
4. A system in accordance with claim 1, further comprising:
a second memory interface operable to retrieve Hough transform values from
the plurality of Hough transform sub-space memories; and
a post-processor, operable to process the Hough transform values.
5. A system in accordance with claim 1, wherein the plurality of Hough transform sub-space memories comprise non-overlapping regions of a single physical memory.
6. A system in accordance with claim 5, wherein the plurality of Hough transform sub-space memories are dynamically allocated from the single physical memory.
7. A method for parallel computation of a transform of an array of data values to a transform space, the method comprising:
initializing a transform space memory;
retrieving a data value from the array of data values;
partitioning the transform space memory into a plurality of transform sub-space memories;
passing the data value to a plurality of processors, each processor associated with a transform sub-space memory of the plurality of transform sub-space memories;
each processor of the plurality of processors updating elements of the transform stored in the associated transform sub-space memory dependent upon the data value; and
providing an output dependent upon elements of the transform space.
8. A method in accordance with claim 7, wherein updating elements of the transform comprises:
determining a set of elements in the transform sub-space that are affected by the data value; and
adding the data value to each element in the set of affected elements.
9. A method in accordance with claim 7, wherein the transform comprises a Hough transform that utilizes a curve parameterized by the equations (x,p) =0, where p is a parameter vector in the transform space, x is a position vector in the data array, and s is a function and wherein the data value at position xi is used to update transform parameters p satisfying the equation s(xi,p)=0.
10. A method in accordance with claim 9, wherein the data array comprises pixel values determined by preprocessing an image to detect foreground elements.
11. A method in. accordance with claim 9, wherein the data array comprises pixel values determined by preprocessing an image to detect edges of objects in the image.
12. A method in accordance with claim 9, further comprising searching the elements of the Hough transform to find the largest value in the Hough transform elements and wherein providing an output dependent upon the elements of the Hough transform comprises outputting the largest value and its location in the Hough transform.
13. The method in accordance with claim 7, wherein the parallel computation is of a Hough transform and further comprising:
prior to initializing, quantizing the transform space of the Hough transform into a plurality of discrete parameter values, each parameter value have K elements and the plurality of discrete parameter values defining a K-dimensional discrete transform space.
14. A method in accordance with claim 13, wherein the transform memory is partitioned into a plurality of Hough transform sub-space memories such that computation of the Hough transform is distributed among the processor of the plurality of processors in accordance with a specified distribution.
15. A method in accordance with claim 13, wherein the transform memory is partitioned into a plurality of Hough transform sub-space memories such that computation of the Hough transform is approximately evenly distributed among the processor of the plurality of processors.
16. A method for identifying a high level feature of an image represented as an input array of pixel values, comprising:
normalizing the input array of pixel values;
pre-processing the array of normalized pixel values to provide an array of data values;
segmenting the array of data values into one or more regions of interest;
identifying low level features in the array of data values;
partitioning the transform space of a Hough transform into a plurality of sub-spaces;
calculating, in parallel, the Hough transform of the one or more regions of interest in the plurality of sub-spaces;
searching the Hough transform space to identify the high level feature of the image; and
outputting parameters to specify the high level feature of the image.
17. A method in accordance with claim 16, wherein identifying low level features in the array of data values comprises detecting edges of objects in the image.
18. A method in accordance with claim 16, wherein the high level feature is an eye position.
19. A method in accordance with claim 16, wherein the array of pixel values define a video frame, the method further comprising:
post-processing the identified high level feature to check for consistency between adjacent video frames.
20. A system for computing a Hough transform comprising:
a plurality of processing means, capable of parallel operation, each operable to calculate a sub-set of elements of a Hough transform;
a plurality of sub-space storage means, each associated with a processing means of the plurality of processing means and operable to store a subset of elements of the Hough transform;
a means for distributing a pixel location value to each processing means of the plurality of processing means; and
a means for outputting a result dependent upon the elements of the Hough transform.
21. A system in accordance with claim 20, further comprising a post-processing means for searching the elements of the Hough transform to detect the largest transform elements.
22. A system in accordance with claim 20, wherein the plurality of sub-space storage means comprises non-overlapping regions of a memory.
23. A system in accordance with claim 22, wherein the non-overlapping regions of a memory are allocated dynamically.
24. A Hough transform method for tracking eye movements, comprising:
receiving a video frame comprising an array of first data values;
preprocessing the array of first data values to provide a plurality of second data values;
calculating a Hough transform of the plurality of second data values for elliptical primitive curves;
identifying eye positions by detecting ellipses using the Hough transform; and
identifying iris positions by detecting circles using the Hough transform of elliptical primitive curves; wherein calculating a Hough transform of the plurality of second data values comprises:
initializing a Hough transform memory;
retrieving a data value from the plurality of second data values;
passing the data value to a plurality of processors;
associating each processor of the plurality of processors with a Hough transform sub-space memory of the Hough transform memory; and
each processor of the plurality of processors updating elements of the Hough transform stored in the associated Hough transform sub-space memory dependent upon the data value.
25. A method in accordance with claim 24, wherein associating each processor of the plurality of processors with a Hough transform sub-space memory of the Hough transform memory comprises dynamically allocating a Hough transform sub-space memory to each processor to maintain a substantially equal distribution of computation between the plurality of processors.
26. A method in accordance with claim 24, wherein preprocessing the array of first data values to provide a plurality of second data values comprises:
normalizing the array of first data values to provide an array of normalized data values;
filtering the array of normalized data values to provide an array of filtered data values;
segmenting the array of filtered data values to obtain one more regions of interest; and
extracting low level features in the one more regions of interest.
27. A method in accordance with claim 24, wherein identifying eye positions and identifying iris positions further comprises checking for consistency with adjacent video frames.