1. A method for estimating the size of a core section of a semiconductor integrated circuit, wherein the core section includes a plurality of nets, each including a plurality of wires, the method comprising:
calculating, by a processor, an average path length of the wires in each net based on cell quantity, average cell area, total macro area, and cell usage rate to calculate a total net length of the wires of the nets;
estimating, by the processor, a core section area based on the cell quantity, the average cell area, the cell usage rate and Rent’s exponent to calculate usable channel length of the core section, the total net length of the wires being the sum of the lengths of a plurality of first wires extending in a predetermined first direction within the core section and the lengths of a plurality of second wires extending in a second direction perpendicular to the first direction within the core section, and the usable channel length being the sum of a channel length in the first direction and a channel length in the second direction within the core section;
calculating, by the processor, a total length of the first wires within the core section;
calculating, by the processor, a total length of the second wires within the core section; and
determining, by the processor, the size of the core section, which is the minimal area that satisfies conditions of the total net length of the wires being less than or equal to the usable channel length within the core section, the total length of the first wires being less than or equal to the channel length in the first direction within the core section, and the total length of the second wires being less than or equal to the channel length in the second direction within the core section.
2. The method according to claim 1, further comprising:
determining, by the processor, whether the conditions are satisfied; and
changing, by the processor, the layout parameter and repeating said calculating the total net length of the wires of the nets and usable channel lengths, the total length of the first wires, and the total length of the second wires, and said determining the size of the core section until the conditions are satisfied.
3. The method according to claim 1, wherein the core section is provided with a plurality of wire layers, each wire layer including at least one circuit block, the nets are each arranged on one of the wire layers, each net having paths, the quantity of which is in accordance with the fan-out of the net, the layout parameter includes an aspect ratio of each circuit, and the circuit information includes the fan-out of each net said calculating the total net length of the wires includes:
calculating, by the processor, the net length of each net based on the average path length and fan-out of each net to calculate the total net length of the nets and
calculating the lengths of the first wires and the lengths of the second wires based on the calculated total net length and the aspect ratio of each circuit block.
4. The method according to claim 1, wherein said calculating the usable channel length of the core section includes:
calculating, by the processor, a routing prohibition channel length of each wire layer;
calculating, by the processor, the usable channel length of each wire layer from the routing prohibition channel length and a maximum channel usage rate, which is in accordance with the area of the estimated area, to calculate the total usable channel length of the wire layers;
calculating, by the processor, the usable channel length in the first direction by totaling the usable channel length of the first wire layers having wires arranged along the first direction; and
calculating, by the processor, the usable channel length in the second direction by totaling the usable channel length of the second wire layers having wires arranged along the second direction.
5. A method for estimating the size of a chip for a semiconductor integrated circuit provided with at least one core section and a plurality of power supply pads, the core section including a plurality of nets, each having a plurality of wires, and each of the power supply pads being connected to the core section via an IO buffer having a predetermined current capacity, the method comprising:
calculating, by a processor, an average path length of the wires in each net based on cell quantity, average cell area, total macro area and cell usage rate to calculate a total net length of the wires of the nets;
estimating, by the processor, a core section area based on the cell quantity, the average cell area, the cell usage rate and Rent’s exponent to calculate the usable channel length of the core section, the total net length of the wires being the sum of the lengths of a plurality of first wires extending in a predetermined first direction within the core section and the lengths of a plurality of second wires extending in a second direction perpendicular to the first direction within the core section, and the usable channel length being the sum of a channel length in the first direction and a channel length in the second direction within the core section;
determining, by the processor, the size of the core section, which is the minimal area that satisfies conditions of the total net length of the wires being less than or equal to the usable channel length within the core section, the total length of the first wires being less than or equal to the channel length in the first direction within the core section, and the total length of the second wires being less than or equal to the channel length in the second direction within the core section;
performing, by the processor, a power supply network analysis of the core section based on power consumption information of the core section and power supply wire resistance information, which includes resistances between the nodes, to calculate voltage values of the nodes within the core section;
calculating, by the processor, current values between the nodes from the voltage values of the nodes and the resistances between the nodes;
calculating, by the processor, current values of the power supply pads from the current values between the nodes;
determining, by the processor, whether there is a power supply pad for which current value exceeds the predetermined current capacity;
eliminating or adding, by the processor, a power supply pad in accordance with the determination result and determining the quantity and locations of the power supply pads to calculate the area of an IO region in accordance with the determined quantity; and
totaling, by the processor, the size of the core section and the area of the IO region to calculate an estimated size of the chip.
6. An apparatus for designing a semiconductor integrated circuit having a core section provided with a plurality of nets, each including a plurality of wires, the apparatus comprising:
a storage device which stores cell quantity, average cell area, total macro area, and cell usage rate that are used to design the semiconductor integrated circuit; and
a data processor in communication with the storage device,
in which the data processor:
calculates an average path length of the wires in each net based on the cell quantity, the average cell area, the total macro area, and the cell usage rate to calculate a total net length of the wires of the nets;
estimate a core section area based on the cell quantity, the average cell area, the cell usage rate and Rent’s exponent to calculate usable channel length of the core section, the total net length of the wires being the sum of the lengths of a plurality of first wires extending in a predetermined first direction within the core section and the lengths of a plurality of second wires extending in a second direction perpendicular to the first direction within the core section, and the usable channel length being the sum of a channel length in the first direction and a channel length in the second direction within the core section; and
determines the size of the core section, which is the minimal area that satisfies conditions including the total net length of the wires being less than or equal to the usable channel length within the core section, the total length of the first wires being less than or equal to the channel length in the first direction within the core section, and the total length of the second wires being less than or equal to the channel length in the second direction within the core section.
7. An apparatus for designing a semiconductor integrated circuit provided with a core section and a plurality of power supply pads, the core section including a plurality of nodes and a plurality of nets, each net having a plurality of wires, and each of the power supply pads being connected to the core section via an IO buffer having a predetermined current capacity, the apparatus comprising:
a storage device which stores power consumption information of the core section, power supply wire resistance information, which includes resistances between the nodes, and cell quantity, average cell area, total macro area, and cell usage rate; and
a data processor in communication with the storage device,
in which the data processor:
calculates an average path length of the wires in each net based on cell quantity, average cell area, total macro area and cell usage rate to calculate a total net length of the wires of the nets;
estimates a core section area based on the cell quantity, the average cell area, the cell usage rate and Rent’s exponent to calculate usable channel length of the core section, the total net length of the wires being the sum of the lengths of a plurality of first wires extending in a predetermined first direction within the core section and the lengths of a plurality of second wires extending in a second direction perpendicular to the first direction within the core section, and the usable channel length being the sum of a channel length in the first direction and a channel length in the second direction within the core section;
determines the size of the core section, which is the minimal area that satisfies conditions of the total net length of the wires being less than or equal to the usable channel length within the core section, the total length of the first wires being less than or equal to the channel length in the first direction within the core section, and the total length of the second wires being less than or equal to the channel length in the second direction within the core section;
performs a power supply network analysis of the core section by referring to the determined size of the core section, the power consumption information, and the power supply wire resistance information to calculate voltage values of the nodes within the core section;
calculates current values between the nodes from the voltage values of the nodes and the resistances between the nodes;
calculates current values of the power supply pads from the current values between the nodes;
determines whether there is a power supply pad for which current value exceeds the current capacity of the associated IO buffer; and
eliminates or adds a power supply pad in accordance with the result of the determination to determine the quantity and locations of the power supply pads.
8. A non-transitory computer-readable storage medium comprising computer instructions stored thereon for estimating the size of a core section of a semiconductor integrated circuit, wherein the core section includes a plurality of nets, each including a plurality of wires, the computer instructions when executed by a computer performing operations including:
calculating an average path length of the wires in each net based on cell quantity, average cell area, total macro area, and cell usage rate to calculate a total net length of the wires of the nets;
estimating a core section area based on the cell quantity, the average cell area, the cell usage rate and Rent’s exponent to calculate usable channel length of the core section, the total net length of the wires being the sum of the lengths of a plurality of first wires extending in a predetermined first direction within the core section and the lengths of a plurality of second wires extending in a second direction perpendicular to the first direction within the core section, and the usable channel length being the sum of a channel length in the first direction and a channel length in the second direction within the core section;
determining the size of the core section, which is the minimal area that satisfies conditions of the total net length of the wires being less than or equal to the usable channel length within the core section, the total length of the first wires being less than or equal to the channel length in the first direction within the core section, and the total length of the second wires being less than or equal to the channel length in the second direction within the core section.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to:
obtain one or more parameters of a vehicle;
obtain environmental conditions outside of the vehicle;
calculate a speed in which the vehicle should traverse a portion of a road, the calculating being based on the one or more parameters of the vehicle and the environmental conditions outside of the vehicle; and
provide the calculated speed to the vehicle.
2. The method of claim 1, wherein the environmental conditions include at least one of a road condition in which the vehicle will traverse and weather conditions.
3. The method of claim 1, wherein the one or more parameters of the vehicle includes at least one of current speed, tire conditions, brake pad conditions, current weight of vehicle, weight of trailer if any, number of axles, and safety features of the vehicle.
4. The method of claim 1, wherein the environmental conditions are obtained from one or more sensors and cameras.
5. The method of claim 4, wherein the one or more sensors include at least one of a radar, weather sensors, and road condition sensors, and the cameras include video cameras, each of which provide information to a calculating unit used to calculate the calculated speed.
6. The method of claim 1, wherein the calculating of the speed is further based on at least one of:
municipal, state andor federal speed limits for a portion of the road in which the vehicle is traversing;
historical information associated with the portion of the road in which the vehicle is traversing; and
information obtained by user input.
7. The method of claim 1, wherein the providing the calculated speed to the vehicle is displayed on an electronic road display and, further comprising providing other information to display on the electronic road display.
8. The method of claim 7, wherein the other information is at least one of vehicle identification, road conditions, weather conditions and road configuration.
9. The method of claim 1, wherein the providing the calculated speed is transmitted directly to the vehicle.
10. The method of claim 1, wherein a service provider at least one of creates, maintains, deploys and supports the computer infrastructure.
11. The method of claim 1, wherein steps of claim 1 are provided by a service provider on a subscription, advertising, andor fee basis.
12. A system implemented in hardware, comprising:
one or more sensors which are configured to obtain environmental conditions;
one or more transceivers which are configured to obtain at least one vehicle parameter of a vehicle traversing a portion of a road; and
a calculating unit which is configured to calculate a speed in which the vehicle should traverse the portion of the road, the calculating being based on the environmental conditions and the at least one vehicle parameter.
13. The system of claim 12, wherein the sensors are configured to obtain weather conditions, vehicle trajectory and road conditions.
14. The system of claim 12, further comprising monitoring stations for obtaining weather conditions, vehicle trajectory and road conditions used to calculate the calculated speed.
15. The system of claim 12, further comprising an electronic display, which is configured to receive and display the calculated speed of the vehicle.
16. The system of claim 12, further comprising a transmitting unit to transmit the calculated speed directly to the vehicle.
17. The system of claim 12, wherein the calculating unit calculates the speed in which the vehicle should traverse the portion of the road using any one of:
municipal, state andor federal speed limits for the portion of the road in which the vehicle is traversing;
historical information associated with the portion of the road in which the vehicle is traversing; and
information obtained by user input.
18. The system of claim 12, wherein the calculating unit is provided on a central service server and the one or more sensors are remotely positioned from the central service server.
19. The system of claim 12, wherein the calculating unit is provided with a display unit for displaying the calculated speed.
20. The system of claim 12, wherein the calculating unit periodically updates the calculated speed and provides the updated calculated speed to the vehicle, as it is traversing different portions of the road.
21. A computer program product comprising a computer usable storage medium having readable program code embodied in the storage medium, the computer program product includes at least one component operable to:
calculate a speed that a vehicle should be traveling along a portion of a roadway, based on obtained environmental conditions and at least one vehicle parameter of a vehicle traversing the portion of the roadway; and
provide the calculated speed to the vehicle.
22. The computer program product of claim 21, further operable to calculate the speed based on historical information previously obtained for calculating speed for at least one of the vehicle and other vehicles.
23. A computer system for calculating a vehicle’s recommended speed, the system comprising:
a CPU, a computer readable memory and a computer readable storage media;
first program instructions to obtain vehicle information;
second program instructions to obtain conditions outside of the vehicle;
third program instructions to calculate the recommended speed of the vehicle while traverse a portion of a road, the calculating being based on the obtained vehicle information, conditions outside of the vehicle, road configuration and historical information related to the portion of the road;
fourth program instructions to provide the recommended speed to the vehicle by displaying it on a roadside sign with additional information comprising at least one of: vehicle identification, weather conditions, road conditions, and road configuration,
wherein the first, second, third and fourth program instructions are stored on the computer readable storage media for execution by the CPU via the computer readable memory.
24. The computer system of claim 23, further comprising fifth program instructions to provide the recommended speed directly to an occupant of the vehicle.
25. A method of deploying a system for calculating a recommended speed of a vehicle comprising:
providing a computer infrastructure, being operable to:
obtaining vehicle information, environmental conditions and road conditions for a portion of a road in which the vehicle is traversing;
calculating the recommended speed of the vehicle for the portion of the road, the calculating being based on the obtained vehicle information, environmental conditions and road conditions; and
updating the recommended speed as the vehicle is traversing the portion of the road based on a location of the vehicle on the portion of the road.