1. A computer program product for detecting a Decimal Floating Point Quantum exception, the computer program product comprising:
a computer readable storage medium having program code embodied therewith, the program code readable by a computer processor to perform a method comprising:
executing, by the processor, an instruction, the executing comprising:
obtaining, by at least one processor of a processing environment, at least one decimal floating point operand;
performing a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result having a quantum;
determining a preferred quantum based upon the operation and on the at least one decimal floating point operand;
based on determining that the quantum of the decimal floating point result is different from the preferred quantum, providing an output indicating a quantum exception, wherein providing an output indicating a quantum exception comprises:
determining whether a quantum exception mask bit is set;
based on determining that the quantum exception mask bit is not set, storing the decimal floating point result and setting a quantum exception flag bit; and
based on determining that the quantum exception mask bit is set, storing the decimal floating point result and performing a trap operation; and
based on determining that the quantum of the decimal floating point result is the same as the preferred quantum, providing an output without a quantum exception.
2. The computer program product of claim 1, wherein indicating a quantum exception comprises a non trap action, the non trap action occurring when the quantum exception is recognized and a quantum exception mask bit in a Floating Point Control (FPC) register is zero.
3. The computer program product of claim 2, the executing further comprising writing the output to a result register and continuing with normal operation.
4. The computer program product of claim 1, wherein indicating a quantum exception comprises a trap action, the trap action occurring when the quantum exception is recognized and a quantum exception mask bit in a Floating Point Control (FPC) register is one.
5. The computer program product of claim 1, the executing further comprising: writing the output to a result register; setting an exception code; and trapping to a program interrupt handler.
6. The computer program product of claim 1, wherein providing an output without a quantum exception further comprises: writing the result to a register; not setting a flag; not setting an exception code; and continuing with normal operation.
7. The computer program product of claim 1, the method further comprising:
determining whether the quantum exception flag bit is set; and
based on determining that the quantum exception flag bit is set, processing a previously detected quantum exception.
8. A computer system for detecting a Decimal Floating Point Quantum exception, the system comprising:
a memory; and
a processor configured to communicate with the memory, wherein the computer system is configured to perform a method, the method comprising:
executing, by the processor, an instruction, the executing comprising:
obtaining, by at least one processor of a processing environment at least one decimal floating point operand;
performing a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result having a quantum;
determining a preferred quantum based upon the operation and on the at least one decimal floating point operand;
based on determining that the quantum of the decimal floating point result is different from the preferred quantum, providing an output indicating a quantum exception, wherein providing an output indicating a quantum exception comprises:
determining whether a quantum exception mask bit is set;
based on determining that the quantum exception mask bit is not set, storing the decimal floating point result and setting a quantum exception flag bit; and
based on determining that the quantum exception mask bit is set, storing the decimal floating point result and performing a trap operation; and
based on determining that the quantum of the decimal floating point result is the same as the preferred quantum, providing an output without a quantum exception.
9. The system of claim 8, wherein indicating a quantum exception comprises a non trap action, the non trap action occurring when the quantum exception is recognized and a quantum exception mask bit in a Floating Point Control (FPC) register is zero.
10. The system of claim 9, the executing further comprising writing the output to a result register and continuing with normal operation.
11. The system of claim 8, wherein indicating a quantum exception comprises a trap action, the trap action occurring when the quantum exception is recognized and a quantum exception mask bit in a Floating Point Control (FPC) register is one.
12. The system of claim 8, the executing further comprising: writing the output to a result register; setting an exception code; and trapping to a program interrupt handler.
13. The system of claim 8, wherein providing an output without a quantum exception further comprises: writing the result to a register; not setting a flag; not setting an exception code; and continuing with normal operation.
14. The system of claim 8, the method further comprising:
determining whether the quantum exception flag bit is set; and
based on determining that the quantum exception flag bit is set, processing a previously detected quantum exception.
15. A method for executing a machine instruction in a central processing unit, the machine instruction being defined for computer execution according to a computer architecture, said method comprising:
obtaining, by at least one processor of a processing environment, at least one decimal floating point operand;
performing a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result having a quantum;
determining a preferred quantum based upon the operation and on the at least one decimal floating point operand;
based on determining that the quantum of the decimal floating point result is different from the preferred quantum, providing an output indicating a quantum exception, wherein providing an output indicating a quantum exception comprises:
determining whether a quantum exception mask bit is set;
based on determining that the quantum exception mask bit is not set, storing the decimal floating point result and setting a quantum exception flag bit; and
based on determining that the quantum exception mask bit is set, storing the decimal floating point result and performing a trap operation; and
based on determining that the quantum of the decimal floating point result is the same as the preferred quantum, providing an output without a quantum exception.
16. The method of claim 15, wherein indicating a quantum exception comprises a non trap action, the non trap action occurring when the quantum exception is recognized and a quantum exception mask bit in a Floating Point Control (FPC) register is zero.
17. The method of claim 16, further comprising writing the output to a result register and continuing with normal operation.
18. The method of claim 15, wherein indicating a quantum exception comprises a trap action, the trap action occurring when the quantum exception is recognized and a quantum exception mask bit in a Floating Point Control (FPC) register is one.
19. The method of claim 15, further comprising: writing the output to a result register; setting an exception code; and trapping to a program interrupt handler.
20. The method of claim 15, wherein providing an output without a quantum exception further comprises: writing the result to a register; not setting a flag; not setting an exception code; and continuing with normal operation.
21. The method of claim 15, further comprising:
determining whether the quantum exception flag bit is set; and
based on determining that the quantum exception flag bit is set, processing a previously detected quantum exception.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A sample-and-hold circuit, comprising:
a capacitor for storing a voltage input from an outside as an electric charge, and holding a potential thereof;
switches connected to said capacitor, said switches being constituted of a plurality of switches that are connected in series with each other,
wherein a potential difference between both ends of a first switch connected to a side of said capacitor out of the plurality of switches, being set to zero or substantially zero, at least during a time period that said plurality of switches is in the OFF state.
2. A sample-and-hold circuit in accordance with claim 1, wherein said plurality of switches is connected in series with each other, said plurality of switches being simultaneously turned on or off.
3. A sample-and-hold circuit in accordance with claim 1, wherein said first switch is connected to a charge storage electrode of said capacitor.
4. A sample-and-hold circuit in accordance with claim 2, wherein said first switch is connected to a charge storage electrode of said capacitor.
5. A sample-and-hold circuit in accordance with claim 1, further comprising:
an equipotential setting circuit that sets the potential of one end of said first switch wherein another end thereof is connected to said capacitor so that the potential difference between the both ends of said first switch becomes zero or substantially zero.
6. A sample-and-hold circuit in accordance with claim 2, further comprising:
an equipotential setting circuit that sets the potential of one end of said first switch wherein another end thereof is connected to said capacitor so that the potential difference between the both ends of said first switch becomes zero or substantially zero.
7. A sample-and-hold circuit in accordance with claim 1, wherein each of said plurality of switches or said capacitor is formed of a MOS transistor.
8. A sample-and-hold circuit in accordance with claim 2, wherein each of said plurality of switches or said capacitor is formed of a MOS transistor.
9. A sample-and-hold circuit in accordance with claim 5, wherein said equipotential setting circuit comprising:
a differential amplifier having a first input terminal, a second input terminal, and an output terminal for outputting a voltage obtained by amplifying the potential difference between said first and second input terminals; and
a second switch for connecting an interconnection node of said plurality of switches and said first input terminal,
wherein one end of said capacitor is connected to said second input terminal, the other end thereof is connected to said output terminal, and the interconnection node of said plurality of switches and said first input terminal are connected by said second switch, during the time period that said plurality of switches is in the OFF state.
10. A sample-and-hold circuit in accordance with claim 6, wherein said equipotential setting circuit comprising:
a differential amplifier having a first input terminal, a second input terminal, and an output terminal for outputting the voltage obtained by amplifying a potential difference between said first and second input terminals; and
a second switch for connecting an interconnection node of said plurality of switches and said first input terminal,
wherein one end of said capacitor is connected to said second input terminal, the other end thereof is connected to said output terminal, and the interconnection node of said plurality of switches and said first input terminal are connected by said second switch, during the time period that said plurality of switches is in the OFF state.
11. A sample-and-hold circuit in accordance with claim 5, wherein said equipotential setting circuit further comprising:
a buffer amplifier that amplifies a voltage at an interconnection node between one end of said capacitor and the input terminal of said amplifier, outputs the amplified voltage to the output terminal thereof, and has an amplification factor of 1; and
a switch that connects the interconnection node of said plurality of switches and the output terminal of said buffer amplifier, during the time period that said plurality of switches is in the OFF state.
12. A sample-and-hold circuit in accordance with claim 6, wherein said equipotential setting circuit further comprising:
a buffer amplifier that amplifies a voltage at an interconnection node between one end of said capacitor and the input terminal of said amplifier, outputs the amplified voltage to the output terminal thereof, and has an amplification factor of 1; and
a switch that connects the interconnection node of said plurality of switches and the output terminal of said buffer amplifier, during the time period that said plurality of switches is in the OFF state.