1. A method of producing a reference bandgap voltage, the method comprising:
generating a proportional to absolute temperature (PTAT) voltage difference based on respective voltages across a first pair of diodes;
sampling and scaling the PTAT voltage difference using a switched-capacitor amplifier;
using the switched-capacitor amplifier to sample and scale a difference in voltages across a second pair of diodes, one of which is biased with a PTAT current and the other of which is biased with a current that exhibits little or no linear temperature dependency; and
combining the scaled voltage differences with a voltage corresponding to a voltage across the diode that is biased with the PTAT current so as to at least partially compensate for linear and non-linear temperature-dependent components of the voltage across the diode.
2. The method of claim 1 wherein the first pair of diodes includes a first diode and a second diode, and wherein the second pair of diodes includes the first diode and a third diode.
3. The method of claim 2 wherein the first diode is biased with the PTAT current.
4. The method of claim 2 wherein the current exhibiting little or no linear temperature dependency that is used to bias the third diode is generated by superimposing an output voltage from the switched-capacitor amplifier onto a resistance and mirroring a current flowing through the resistance.
5. The method of claim 1 using a two-phase clock to sample and scale the PTAT voltage difference and to sample and scale the difference in voltages across the second pair of diodes.
6. The method of claim 5 wherein the PTAT voltage difference is scaled based, at least in part, on a first capacitance, and wherein the difference in voltages across the second pair of diodes is scaled based, at least in part, on a second capacitance.
7. The method of claim 2 including:
using a two-phase clock to sample and scale the PTAT voltage difference between the voltages across the first and second diodes and to sample and scale the difference in voltages across the first and third diodes; and
scaling the PTAT voltage difference based, at least in part, on a first capacitance, and scaling the difference in voltages across the first and third diodes based, at least in part, on a second capacitance,
wherein signals from the clock control switches so that during a first clock phase, an anode of the first diode is coupled electrically to each of first and second capacitances, and so that during a second clock phase, an anode of the second diode is coupled electrically to the first capacitance and an anode of the third diode is coupled electrically to the second capacitance.
8. A circuit for producing a reference bandgap voltage, the circuit comprising:
a first pair of diodes;
a second pair of diodes, one of which is biased with a PTAT current and the other of which is biased with a current that exhibits little or no linear temperature dependency;
circuitry to generate a proportional to absolute temperature (PTAT) voltage difference based on respective voltages across the first pair of diodes;
a switched-capacitor amplifier to sample and scale the PTAT voltage difference and to sample and scale a difference in voltages across the second pair of diodes; and
circuitry to combine the scaled voltage differences with a voltage corresponding to a voltage across the diode that is biased with the PTAT current so as to at least partially compensate for linear and non-linear temperature-dependent components of the voltage across the diode.
9. The circuit of claim 8 wherein the first pair of diodes includes a first diode and a second diode, and wherein the second pair of diodes includes the first diode and a third diode.
10. The circuit of claim 9 wherein the first diode is biased with the PTAT current.
11. The circuit of claim 9 further including a resistance and a current mirror, wherein an output of the switch-capacitor amplifier is superimposed on the resistance to generate a current which is mirrored by the current mirror to generate the current that exhibits little or no linear temperature dependency.
12. The circuit of claim 8 including a plurality of switches and a two-phase clock to control respective states of the switches so as to sample and scale the PTAT voltage difference and to sample and scale the difference in voltages across the second pair of diodes.
13. The circuit of claim 12 including a first capacitance and a second capacitance, wherein the PTAT voltage difference is scaled based, at least in part, on the first capacitance, and wherein the difference in voltages across the second pair of diodes is scaled based, at least in part, on the second capacitance.
14. A circuit for producing a reference bandgap voltage, the circuit comprising:
a first diode biased with a PTAT current;
a second diode;
a third diode biased with a current that exhibits substantially no linear temperature dependency;
circuitry to generate a proportional to absolute temperature (PTAT) voltage difference based on respective voltages across the first and second diodes;
a switched-capacitor amplifier to sample and scale the PTAT voltage difference and to sample and scale a difference in voltages across the first and third diodes; and
circuitry to combine the scaled voltage differences with a voltage corresponding to a voltage across the diode that is biased with the PTAT current so as to at least partially compensate for linear and non-linear temperature-dependent components of the voltage across the diode.
15. The circuit of claim 14 including a plurality of switches and a two-phase clock to control respective states of the switches so as to sample and scale the PTAT voltage difference and to sample and scale the difference in voltages across the first and third diodes.
16. The circuit of claim 15 including a first capacitance and a second capacitance, wherein the PTAT voltage difference is scaled based, at least in part, on the first capacitance, and wherein the difference in voltages across the first and third diodes is scaled based, at least in part, on the second capacitance.
17. The circuit of claim 16 wherein the clock controls the switches so that during a first clock phase, each of the first and second capacitances is coupled electrically to an anode of the first diode, and during a second clock phase, the first capacitance is coupled electrically to an anode of the second diode, and the second capacitance is coupled electrically to an anode of the third diode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A nonvolatile memory comprising:
a deep well formed on a substrate;
a first well formed within the deep well;
a second well formed separately from the first well within the deep well;
a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well; and
a second MOSFET formed on the second well.
2. The nonvolatile memory of claim 1, wherein the deep well comprises a conductive deep N-well, the first and second wells comprise a conductive P well, and the first and second MOSFETs are a conductive NMOS.
3. The nonvolatile memory of claim 1, wherein at least one of the first and second wells is shared between adjacent memory cells in the nonvolatile memory.
4. The nonvolatile memory of claim 1, wherein the nonvolatile memory applies a first voltage for recording data to the first MOSFET, applies a preset voltage to the second well and the second MOSFET, constantly maintains a voltage of the second well, and applies a different voltage to a sourcedrain of the second MOSFET from that of an adjacent memory cell to record data only in a selected memory cell.
5. The nonvolatile memory of claim 1, wherein the nonvolatile memory applies a first voltage for recording data to at least one of a source region, a drain region and a well region of the first MOSFET so as to record data in the memory, applies a preset voltage to the second well shared between a memory cell included in the nonvolatile memory and a memory cell adjacent to the memory cell, applies a preset voltage to at least one of a source region and a drain region of the second MOSFET, and controls to 0 V or float a source region and a drain region of a second MOSFET included in a memory cell not selected for recording the data, so that electrons are injected into a floating gate of the second MOSFET by tunneling.
6. The nonvolatile memory of claim 1, wherein the nonvolatile memory applies a first voltage for recording data to at least one of a source region, a drain region and a well region of the first MOSFET so as to record data in the memory, applies a voltage of 0 V to the second well shared between a memory cell included in the nonvolatile memory and a memory cell adjacent to the memory cell, applies a voltage of 0 V to a source region of the second MOSFET, applies a preset voltage to a drain region of the second MOSFET, and controls to 0 V or float a drain region of a second MOSFET included in a memory cell not selected for recording the data, so that channel hot electrons generated in a channel region of the second MOSFET are injected into a floating gate of the second MOSFET.
7. The nonvolatile memory of claim 1, wherein the nonvolatile memory applies a second voltage for deleting data to at least one of a source region, a drain region and a well region of the first MOSFET so as to delete data recorded in the memory, applies a preset voltage to the second well shared between a memory cell included in the nonvolatile memory and a memory cell adjacent to the memory cell, applies a preset voltage to at least one of a source region and a drain region of the second MOSFET, and controls to 0 V or float a source region and a drain region of a second MOSFET included in a memory cell not selected for deleting the data, so that electrons are removed from a floating gate of the second MOSFET by tunneling.
8. The nonvolatile memory of claim 1, wherein the nonvolatile memory applies a second voltage for deleting data to at least one of a source region, a drain region and a well region of the first MOSFET so as to delete data recorded in the memory, applies a voltage of 0 V or a preset voltage to the second well shared between a memory cell included in the nonvolatile memory and a memory cell adjacent to the memory cell, applies a voltage of 0 V to a source region of the second MOSFET, applies a preset voltage to a drain region of the second MOSFET, and controls to 0 V or float a drain region of a second MOSFET included in a memory cell not selected for deleting the data, so that a negative voltage is induced in a floating gate of the second MOSFET and holes generated in a channel region of the second MOSFET by impact ionization are injected into the floating gate of the second MOSFET.
9. The nonvolatile memory of claim 1, wherein the first MOSFET comprises at least one of one or more n+ type diffusion regions and one or more p+ type diffusion regions.
10. The nonvolatile memory of claim 1, further comprising a selector transistor formed on the second well.
11. A nonvolatile memory comprising:
a first deep well formed on a substrate;
a first well formed within the first deep well;
a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well;
a second deep well formed separately from the first deep well on the substrate;
a second well formed within the second deep well; and
a second MOSFET formed on the second well.
12. The nonvolatile memory of claim 11, wherein the first and second deep wells comprise a conductive deep N-well, the first and second wells comprise a conductive P well, and the first and second MOSFETs are a conductive NMOS.
13. The nonvolatile memory of claim 11, further comprising a third well formed between the first deep well and the second deep well to separate the first deep well from the second deep well.
14. The nonvolatile memory of claim 11, wherein at least one of the first and second wells is shared between adjacent memory cells in the nonvolatile memory.
15. The nonvolatile memory of claim 11, further comprising a selector transistor formed on the second well.
16. The nonvolatile memory of claim 11, wherein the nonvolatile memory applies a preset voltage to a shared well region of the second MOSFET and applies a different voltage to a source and a drain of the second MOSFET included in a selected memory cell from that of an adjacent memory cell to record data only in the selected memory cell or to delete data recorded in the selected memory cell.