1. A circuit, comprising:
a digitization portion coupled to receive a shaped signal and to provide a digitized output; and
an error determination portion coupled to the digitization portion, the error determination portion including:
a digital-to-analog converter configured to convert the digitized output to an intermediate analog signal;
a first combiner configured to determine an error based on a combination of a gained signal and the intermediate analog signal;
an analog-to-digital converter configured to convert the combination of the gained signal and the intermediate analog signal to an intermediate digital signal; and
a noise transfer function component configured to apply a noise transfer function to the intermediate digital signal to provide a transformed error, the transformed error being combined with the digitized output to provide a corrected digital output.
2. The circuit as recited in claim 1, wherein the digitization portion includes:
an analyzer coupled to receive the shaped signal and to provide an analyzer output having one of a first value and a second value, the analyzer output having the first value when the shaped signal is within a first range, and the analyzer output having the second value when the shaped signal is within a second range; and
a sampling component coupled to receive the analyzer output and a clock signal, and to provide the digitized output based on the clock signal.
3. The circuit as recited in claim 2, wherein the analyzer comprises a comparator.
4. The circuit as recited in claim 1, further comprising a shaping component to provide the shaped signal, and wherein the shaping component is characterized by a complex transfer function, and wherein the noise transfer function is an inverse transformation of the complex transfer function.
5. The circuit as recited in claim 1, wherein the error determination portion further includes:
a low pass filter configured to filter the combination of the gained signal and the intermediate analog signal, and
a second gain component configured to apply a second gain to an output from the low pass filter prior to conversion by the analog-to-digital converter.
6. The circuit as recited in claim 1, further comprising a second combiner configured to combine the digitized output with an initial input signal to provide an analog input signal.
7. The circuit as recited in claim 1, further comprising a shaping component to provide the shaped signal, the shaping component having at least one of a filter and a multi-stage noise shaping component.
8. An electronic device, comprising:
a processor; and
a communication component operatively coupled to the processor and configured to at least one of receive and transmit communication signals, the communication component including a modulator component having:
a digitization portion coupled to receive a shaped signal and to provide a digitized output; and
an error determination portion coupled to the digitization portion, the error determination portion including:
a digital-to-analog converter configured to convert the digitized output to an intermediate analog signal;
a first combiner configured to determine an error based on a combination of a gained signal and the intermediate analog signal;
an analog-to-digital converter configured to convert the combination of the gained signal and the intermediate analog signal to an intermediate digital signal; and
a noise transfer function component configured to apply a noise transfer function to the intermediate digital signal to provide a transformed error, the transformed error being combined with the digitized output to provide a corrected digital output.
9. The electronic device as recited in claim 8, wherein the digitization portion includes:
an analyzer coupled to receive the shaped signal and to provide an analyzer output having one of a first value and a second value, the analyzer output having the first value when the shaped signal is within a first range, and the analyzer output having the second value when the shaped signal is within a second range; and
a sampling component coupled to receive the analyzer output and a clock signal, and to provide the digitized output based on the clock signal.
10. The electronic device as recited in claim 8, wherein the error determination portion further includes:
a low pass filter configured to filter the combination of the gained signal and the intermediate analog signal, and
a second gain component configured to apply a second gain to an output from the low pass filter prior to conversion by the analog-to-digital converter.
11. The electronic device as recited in claim 8, further comprising a shaping component, the shaping component having at least one of a filter, and a multi-stage noise shaping component.
12. A method, comprising:
digitizing a shaped signal to provide a digitized signal;
applying a gain to the shaped signal to provide a gained signal;
converting the digitized signal to an intermediate analog signal;
determining an error based on a combination of the gained signal and the intermediate analog signal;
converting the combination of the gained signal and the intermediate analog signal to an intermediate digital signal; and
applying a noise transfer function to the intermediate digital signal to provide a transformed error, the transformed error being combined with the digitized signal to provide a corrected digital output.
13. The method as recited in claim 12, wherein digitizing the shaped signal includes:
analyzing the shaped signal;
providing an analyzer output having one of a first value and a second value, the analyzer output having the first value when the shaped signal is within a first range, and the analyzer output having the second value when the shaped signal is within a second range; and p1 sampling the analyzer output at a clock frequency to provide the digitized signal.
14. The method as recited in claim 12, wherein determining the error further includes:
low-pass filtering the combination of the gained signal and the intermediate analog signal, and
applying a second gain to an output from the low-pass filtering prior to conversion to the intermediate digital signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A processor comprising:
scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements;
the scheduling circuitry having at least one time slot table accessible thereto;
wherein the scheduling circuitry is configured for utilization of the at least one time slot table in scheduling the data blocks for transmission, the time slot table comprising a plurality of locations, each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements.
2. The processor of claim 1 wherein the time slot table is stored at least in part in an internal memory of the processor.
3. The processor of claim 1 wherein the time slot table is stored at least in part in an external memory coupled to the processor.
4. The processor of claim 1 wherein a given one of the locations in the time slot table stores in a first portion thereof an identifier of a first one of the transmission elements that has requested transmission of a block of data in the corresponding time slot and stores in a second portion thereof an identifier of a second one of the transmission elements that has requested transmission of a block of data in the corresponding time slot.
5. The processor of claim 1 wherein one or more of the data blocks comprise data packets.
6. The processor of claim 1 wherein the scheduling circuitry provides dynamic maintenance of the time slot table such that identifiers of requesting transmission elements are entered into the table locations on a demand basis.
7. The processor of claim 1 wherein the identifiers of the transmission elements comprise a structure for allowing a given one of the transmission element identifiers to be linked to another of the transmission element identifiers.
8. The processor of claim 7 wherein in the event of a collision between multiple transmission elements requesting a given one of the time slots, an identifier of a first one of the requesting transmission elements is entered into a first portion of the corresponding location in the time slot table, an identifier of a final one of the requesting elements is entered into a second portion of the corresponding location in the time slot table, and an identifier of an additional one of the requesting elements is linked to at least one of the identifier of the first requesting element and the identifier of the second requesting element, a linked list of the multiple requesting elements thereby being created for the corresponding location in the time slot table.
9. The processor of claim 8 wherein upon transmission of a data block from one of the requesting transmission elements in the linked list of elements, a determination is made as to whether there are any further elements linked to that element, and for a given such further element the transmission of a data block therefrom is scheduled.
10. The processor of claim 1 wherein the scheduling circuitry maintains a set of pointers for the time slot table, the set of pointers comprising one or more of:
an actual pointer pointing to a location in the time slot table corresponding to actual time;
a head pointer pointing to a first element of a linked list of multiple requesting transmission elements associated with a given time slot; and
a tail pointer pointing to a final element of the linked list of multiple requesting transmission elements associated with the given time slot.
11. The processor of claim 10 wherein the actual pointer advances by one table location for each of the data blocks transmitted.
12. The processor of claim 10 wherein the head pointer and tail pointer collectively define a dynamic waiting room for at least a subset of the multiple requesting transmission elements associated with the given time slot.
13. The processor of claim 10 further comprising a counter which specifies a number of times a set of one or more of the multiple requesting transmission elements are placed in one or more linked lists of such elements associated with one or more of the time slots.
14. The processor of claim 13 wherein a given requesting transmission element is assigned to a location in the time slot table in accordance with the following equation:
Assigned Time SlotAPWaiting Room DepthRequested Time Slot Interval,
where AP denotes the actual pointer, the waiting room depth is the value of the counter, and the requested time slot interval is the time slot interval requested by the requesting transmission element.
15. The processor of claim 1 further comprising a transmit queue having traffic shaping circuitry coupled thereto, the transmit queue being coupled to the scheduling circuitry and supplying time slot requests from transmission elements to the scheduling circuitry in accordance with a traffic shaping requirement established by the traffic shaping circuitry.
16. The processor of claim 1 wherein the processor comprises the at least one time slot table.
17. The processor of claim 1 wherein the processor comprises a network processor configured to provide an interface for data block transfer between a network and a switch fabric.
18. The processor of claim 1 wherein the processor is configured as an integrated circuit.
19. A method for use in a processor, the method comprising:
scheduling data blocks for transmission from a plurality of transmission elements;
wherein the scheduling step utilizes at least one time slot table to schedule the data blocks for transmission, the time slot table comprising a plurality of locations, each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements.
20. An article of manufacture comprising a machine-readable storage medium for use in conjunction with a processor, the medium storing one or more software programs for use in scheduling data blocks for transmission from a plurality of transmission elements, utilizing at least one time slot table, the time slot table comprising a plurality of locations, each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements, wherein the one or more programs when executed implement the step of scheduling the data blocks for transmission from the plurality of transmission elements.