1. An output preset circuit for an output buffer, comprising:
a latch having a first input terminal receiving a power on reset signal, a second input terminal receiving a voltage of the output buffer, a third input terminal receiving an internal output enable signal and an output terminal outputting a latch output signal; and
an output preset device, comprising:
a pull-up circuit receiving a preset enable signal and the latch output signal, wherein the pull-up circuit increases the voltage of the output buffer from a ground level to a first level when the preset enable signal is active and the latch output signal is at the high level; and
a pull-low circuit receiving the preset enable signal and the latch output signal, wherein the pull-low circuit decreases the voltage of the output buffer from a power voltage level to a second level when the preset enable signal is active and the latch output signal is at the low level, and the first level and the second level are between the power voltage level and the ground level.
2. An output preset circuit according to claim 1, wherein the output buffer further connects an output load and comprises an output driver, and the output load has a first terminal and a second terminal coupled to a ground.
3. An output preset circuit according to claim 2, wherein the pull-up circuit comprises a first inverter having an input terminal receiving the preset enable signal and an output terminal, a NAND gate having a first input terminal coupled to the output terminal of the first inverter, a second input terminal receiving the latch output signal and an output terminal, a second inverter having an input terminal coupled to the output terminal of the NAND gate and an output terminal, and a first switch having a first terminal receiving a power voltage, a second terminal coupled to the first terminal of the output load and a control terminal coupled to the output terminal of the second inverter.
4. An output preset circuit according to claim 3, wherein the pull-low circuit comprises a NOR gate having a first input terminal receiving the preset enable signal, a second input terminal receiving the latch output signal, and an output terminal, a third inverter having an input terminal coupled to the output terminal of the NOR gate and an output terminal, and a second switch having a first terminal coupled to the first terminal of the output load, a second terminal coupled to the ground and a control terminal coupled to the output terminal of the third inverter.
5. An output preset circuit according to claim 4, wherein the first switch is an NMOS, the second switch is a PMOS, the NMOS is turned on when the preset enable signal is at the high level and the latch output signal is at the high level, the PMOS is turned on when the preset enable signal is at the low level and the latch output signal is at the low level, the first level equals to a difference between the power voltage and a threshold voltage of the NMOS, and the second level equals to a threshold voltage of the PMOS.
6. An output preset circuit according to claim 2, wherein the output driver causes a voltage of the output load to increase from the first level to the power voltage level when the preset enable signal is inactive, the latch output signal is at the high level, and the internal output enable signal is active, and the output driver causes the voltage of the output load to decrease from the second level to the ground level when the preset enable signal is inactive, the latch output signal is at the low level, and the internal output enable signal is active.
7. An output preset circuit according to claim 6, wherein the latch output signal at the high level is switched to the low level when the voltage of the output load reaches the power voltage level and the internal output enable signal is active, and the latch output signal at the low level is switched to the high level when the voltage of the output load reaches the ground level and the internal output enable signal is active.
8. An output preset circuit according to claim 6, wherein the output driver outputs a data via the output load, and the preset enable signal goes from inactive to active when an external output enable signal goes low, maintains at active for a predetermined time period, and goes back to inactive after the predetermined time period so as to preset the voltage of the output load.
9. An output preset circuit according to claim 1, wherein the output buffer further connects an output load having a first terminal and a second terminal coupled to a ground.
10. An output preset circuit according to claim 9, wherein the pull-up circuit comprises an AND gate having an enable terminal receiving an preset enable signal, an input terminal receiving the latch output signal and an output terminal, a first switch having a first terminal receiving a power voltage, a second terminal coupled to the first terminal of the output load and a control terminal coupled to the output terminal of the AND gate.
11. An output preset circuit according to claim 10, wherein the pull-low circuit comprises an OR gate having a first input terminal receiving the preset enable signal, a second input terminal receiving the latch output signal and an output terminal, a second switch having a first terminal coupled to the first terminal of the output load, a second terminal coupled to the ground and a control terminal coupled to the output terminal of the OR gate.
12. An output preset circuit according to claim 9, wherein the output buffer further comprises an output driver causes a voltage of the output load to increase from the first level to the power voltage level when the preset enable signal is inactive, the latch output signal is at the high level, and the internal output enable signal is active, and the output driver causes the voltage of the output load to decrease from the second level to the ground level when the preset enable signal is inactive, the latch output signal is at the low level, and the internal output enable signal is active.
13. A controlling method for an output driver circuit, wherein the output driver circuit connects an output load and comprises an output preset circuit having a latch, and the latch generates an output signal, comprising the steps of:
(a) activating a preset enable signal so as to preset a voltage of the output load to be one of a first level increased from a ground level and a second level decreased from a power voltage level, wherein the first level and the second level are between the power voltage level and the ground level;
(b) increasing the voltage of the output load to a high level when the output signal of latch is at the high level;
(c) decreasing the voltage of the output load to a low level when the output signal of latch is at the low level; and
(d) increasing the voltage of the output load from the first level to the power voltage level when the preset enable signal is inactive, the latch output signal is at a high level, and an internal output enable signal received by the latch is active.
14. A controlling method according to claim 13, further comprising a step of: (e) decreasing the voltage of the output load from the second level to the ground level when the preset enable signal is inactive, the latch output signal is at a low level, and the internal output enable signal is active.
15. A controlling method according to claim 14, wherein the step (d) further comprises a step of
(d1) switching the latch output signal from the high level to the low level when the voltage of the output load reaches the power voltage level and the internal output enable signal is active and step (e) further comprises a step of (e1)
switching the latch output signal from the low level to the high level when the voltage of the output load reaches the ground level and the internal output enable signal is active.
16. A controlling method according to claim 13, wherein the output preset circuit further comprises a first switch and a second switch and the step (a) further comprises the steps of:
(a1) switching the preset enable signal from inactive to active when an external output enable signal goes low, maintains at active for a predetermined time period, and goes back to inactive after the predetermined time period so as to preset the voltage of the output load;
(a2) turning the first switch on and the second switch off when the latch output signal is at the high level such that the voltage of the output load is increased from the ground level to the first level; and
(a3) turning the first switch off and the second switch on when the latch output signal is at the low level such that the voltage of the output load is decreased from the power voltage level to the second level.
17. A controlling method according to claim 16, wherein the first switch is an NMOS, the second switch is a PMOS, the first level equals to a difference between the power voltage and a threshold voltage of the NMOS, and the second level equals to a threshold voltage of the PMOS.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of enabling a load balancing system, comprising:
enabling a load balancer to load balance incoming client requests to a plurality of servers;
enabling each server of the plurality of servers to include blank persistence information as at least part of an application level protocol command in a response to a client request;
enabling the load balancer to receive the response to the client request from each of the plurality of servers, and to write persistence information that identifies the respective server in place of the blank persistence information; and
enabling the load balancer to recognize persistence information that is at least part of application level protocol commands included with incoming client requests, and to forward at least some incoming client requests having persistence information to one of the plurality of servers based at least in part on the persistence information included with the incoming client requests.
2. The method of claim 1, wherein the persistence information is included in an HTTP cookie command.
3. A device in a network that includes a plurality of clients and a plurality of servers, comprising:
a mechanism that receives a Hypertext Transport Protocol (HTTP) request from a client; and
a processor for enabling actions, including:
determining a destination server from the plurality of servers, based at least in part on a load balancing determination;
determining if the client previously communicated with the destination server, based at least in part on persistence information included in at least part of an application level protocol command, wherein the application level protocol command includes at least part of an HTTP cookie;
if it is determined that the client previously communicated with the destination server, determining the destination server based at least in part on the persistence information in the HTTP cookie; and
forwarding the HTTP request to the destination server.
4. The device of claim 3, further comprising commanding the client to create the HTTP cookie to include information identifying the destination server.
5. The device of claim 3, further comprising receiving the HTTP cookie from the destination server and inserting the persistence information in the HTTP cookie.
6. The device of claim 3, further comprising receiving the HTTP cookie form the destination server and rewriting at least a portion of the HTTP cookie to include the persistence information.
7. The device of claim 3, wherein the device is operational as at least one of a router, a load balancer, a switch, a server array controller, a server, and an intermediate network device.
8. The device of claim 3, wherein the HTTP cookie includes a key.
9. A system for load balancing communication in a network, comprising:
a plurality of clients;
a plurality of servers; and
a device that includes:
a mechanism arranged to receive a Hypertext Transport Protocol (HTTP) request from a client; and
a processor for enabling actions, including:
determining a destination server from the plurality of servers, based at least in part on a load balancing determination;
determining if the client previously communicated with the destination server, based at least in part on persistence information included in at least part of an application level protocol command, wherein the application level protocol command includes at least part of an HTTP cookie;
if it is determined that the client previously communicated with the destination server, determining the destination server based at least in part on the persistence information in the HTTP cookie; and
forwarding the HTTP request to the destination server.
10. The system of claim 9, further comprising commanding the client to create the HTTP cookie to include information identifying the destination server.
11. The system of claim 9, further comprising receiving the HTTP cookie from the destination server and inserting the persistence information in the HTTP cookie.
12. The system of claim 9, further comprising receiving the HTTP cookie form the destination server and rewriting at least a portion of the HTTP cookie to include the persistence information.
13. The system of claim 9, wherein the device is operational as at least one of a router, a load balancer, a switch, a server array controller, a server, and an intermediate network device.
14. The system of claim 9, wherein the HTTP cookie includes a key.