What is claimed is:
1. A digital circuit comprising:
a scan chain including a plurality of pairs of a selector and a flipflop arranged in cascade, wherein the scan chain performs a capture mode in which in response to a scan enable signal the flipflop captures data from an internal circuit in synchronization with a predetermined clock and a shift mode in which in response to the scan enable signal, one of the data stored in the flipflop and test data input from outside is shifted to a subsequent flipflop in synchronization with the predetermined clock;
a clock generator which generates a clock signal in response to one of the rising edge and the falling edge of the clock pulse of a clock signal input from outside as a trigger; and
a clock selector which receives the clock signal input from outside and the clock signal generated by the clock generator, and selects one of the two clock signals in response to the scan enable signal for switching between the shift mode and the capture mode, and then feeds the selected clock signal to the clock input terminal of at least one flipflop forming the scan chain.
2. A digital circuit according to claim 1, wherein the clock generator generates a clock having one of the falling edge and the rising edge thereof coinciding with one of the rising edge and the falling edge of the clock signal input from outside.
3. A digital circuit according to claim 1, wherein the clock generator generates a clock having one of the falling edge and the rising edge thereof delayed by a predetermined time from the timing of one of the rising edge and the falling edge of the clock signal input from outside.
4. A digital circuit according to claim 2, wherein the clock generator comprises a type D flipflop with an input terminal thereof connected to a high-level voltage, with the clock input terminal thereof receiving an inverted version of the clock signal input from outside, and having a reset terminal, a delay circuit which delays an inverted output of the type D flipflop by a predetermined time, and an OR gate with inputs thereof receiving the clock signal input from outside and the output of the delay circuit, and with the output thereof connected to the reset terminal of the type D flipflop.
5. A digital circuit according to claim 2, wherein the clock generator is a two-input NOR gate with one input receiving the clock signal input from outside, and with the other input receiving an inverted version of a signal which is obtained by delaying the clock signal, input from outside, by a predetermined time.
6. A digital circuit according to claim 3, wherein the clock generator is a two-input NOR gate with one input receiving a signal which is obtained by delaying the clock signal, input from outside, by a predetermined time, and with the other input receiving an inverted version of a signal which is obtained by delaying the clock signal, input from outside, by a predetermined time.
7. A semiconductor device comprising:
a scan chain including a plurality of pairs of a selector and a flipflop arranged in cascade, wherein the scan chain performs a capture mode in which in response to a scan enable signal the flipflop captures data from an internal circuit in synchronization with a predetermined clock and a shift mode in which in response to the scan enable signal, one of the data stored in the flipflop and test data input from outside is shifted to a subsequent flipflop in synchronization with the predetermined clock;
a clock generator which generates a clock signal in response to one of the rising edge and the falling edge of the clock pulse of a clock signal input from outside as a trigger; and
a clock selector which receives the clock signal input from outside and the clock signal generated by the clock generator, and selects one of the two clock signals in response to the scan enable signal for switching between the shift mode and the capture mode, and then feeds the selected clock signal to the clock input terminal of at least one flipflop forming the scan chain.
8. A semiconductor device according to claim 7, wherein the clock generator generates a clock having one of the falling edge and the rising edge thereof coinciding with one of the rising edge and the falling edge of the clock signal input from outside.
9. A semiconductor device according to claim 7, wherein the clock generator generates a clock having one of the falling edge and the rising edge thereof delayed by a predetermined time from the timing of one of the rising edge and the falling edge of the clock signal input from outside.
10. A semiconductor device according to claim 8, wherein the clock generator comprises a type D flipflop with an input terminal thereof connected to a high-level voltage, with the clock input terminal thereof receiving an inverted version of the clock signal input from outside, and having a reset terminal, a delay circuit which delays an inverted output of the type D flipflop by a predetermined time, and an OR gate with inputs thereof receiving the clock signal input from outside and the output of the delay circuit, and with the output thereof connected to the reset terminal of the type D flipflop.
11. A semiconductor device according to claim 8, wherein the clock generator is a two-input NOR gate with one input receiving the clock signal input from outside, and with the other input receiving an inverted version of a signal which is obtained by delaying the clock signal, input from outside, by a predetermined time.
12. A semiconductor device according to claim 9, wherein the clock generator is a two-input NOR gate with one input receiving a signal which is obtained by delaying the clock signal, input from outside, by a predetermined time, and with the other input receiving an inverted version of a signal which is obtained by delaying the clock signal, input from outside, by a predetermined time.
13. A method of testing a semiconductor device including: a scan chain including a plurality of pairs of a selector and a flipflop arranged in cascade, wherein the scan chain performs a capture mode in which in response to a scan enable signal the flipflop captures data from an internal circuit in synchronization with a predetermined clock and a shift mode in which in response to the scan enable signal, one of the data stored in the flipflop and test data input from outside is shifted to a subsequent flipflop in synchronization with the predetermined clock;
a clock generator which generates a clock signal in response to one of the rising edge and the falling edge of the clock pulse of a clock signal input from outside as a trigger; and
a clock selector which receives the clock signal input from outside and the clock signal generated by the clock generator, and selects one of the two clock signals in response to the scan enable signal for switching between the shift mode and the capture mode, and then feeds the selected clock signal to the clock input terminal of at least one flipflop forming the scan chain, the method comprising the steps of:
inputting the clock signal input from outside to the semiconductor device using a tester, and
switching between the shift mode and the capture mode in response to the scan enable signal to test the semiconductor device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory module, on which a plurality of semiconductor memory elements each having terminals for data signals, addresscontrol signals, and clock signals are mounted, the semiconductor memory module comprising:
clock signal lines wired so that said clock signals are in phase with the semiconductor memory elements;
data signal lines wired to the semiconductor memory elements so as to have the same length;
a register setting said addresscontrol signals; and
an addresscommand signal line wired in a daisy-chain shape to said semiconductor memory elements from said register,
wherein each of said semiconductor memory elements has a variable delay circuit with respect to said addresscontrol signals or to said clock signals for taking in said addresscontrol signals, and
a delay amount of said variable delay circuit is set so that the sum of said delay amount and a wiring delay time due to a wiring from said register becomes equal to a wiring delay time from said register to the farthest one among said semiconductor memory elements, or a delay amount of said variable delay circuit is set so that the sum of said delay amount and arrival timing of said clock signals to said semiconductor memory elements becomes equal to a wiring delay time from said register to said semiconductor memory elements.
2. The semiconductor memory module according to claim 1,
wherein each of said semiconductor memory element comprises:
a clock stabilizing circuit that, with respect to said clock signals, reduces jitter and distributes, as a common clock, said clock signals to blocks in said semiconductor memory elements, said common clock being set to an input of a variable delay circuit; and
a register provided therein and setting a value for adjusting a delay time of said variable delay time.
3. The semiconductor memory module according to claim 2,
wherein a value of said register is set by a boundary scan circuit.
4. The semiconductor memory module according to claim 3,
wherein said boundary scan circuit and a non-volatile semiconductor element for boundary scan circuit are provided on said semiconductor memory module.
5. A semiconductor memory module, on which a plurality of semiconductor memory elements each having a terminal for data signals, a terminal for addresscontrol signals, and a terminal for clock signals, the semiconductor memory module comprising:
a clock signal line connected to said terminal for clock signals and transmitting said clock signals;
a data signal line connected to said terminal for data signals and transmitting said data signals;
a register for setting said addresscontrol signals; and
an addresscontrol line connected in a daisy-chain shape to said terminal for addresscontrol signals from said register and transmitting said addresscontrol signals,
wherein each of said semiconductor memory elements has a variable delay circuit for delaying said addresscontrol signals or said clock signals for taking in said addresscontrol signals, and
a delay amount of said variable delay circuit is set so that the sum of said delay amount and a wiring delay time due to a wiring from said register depends on a wiring delay time from said register to the farthest one among said semiconductor memory elements, or a delay amount of said variable delay circuit is set so that the sum of said delay amount and arrival timing of said clock signals to said semiconductor memory elements depends on a wiring delay time from said register to said semiconductor memory elements.