1. A control system for a brushless motor or stepping motor comprising a rotor mounted on a shaft and a stator having a plurality of phase windings powered electrically in a predetermined electrical cycle to cause the rotor to advance, said system comprising:
an indicator device for indicating the mechanical position of the rotor and placed on the shaft thereof;
an optical detector device for measuring the mechanical position of the rotor from the indicator device, and co-operating therewith to form an incremental coder device for the mechanical position of the rotor; and
a motor control assembly comprising processor means for processing signals encoding the mechanical position of the rotor connected to regulator means for regulating the power supply to the plurality of stator windings;
wherein the indicator device for indicating the mechanical position of the rotor comprises at least a first series of indications arranged in a pattern of periodicity that corresponds to a period of an electrical cycle of the motor so as to provide an indication on the phase of the electrical cycle of the stator based on movement of the rotor, and the incremental coder device delivers a synchronizing signal to the processor means, the processing means synchronizing the start of an electrical cycle on the mechanical position of the rotor for all electrical cycles.
2. The system according to claim 1, wherein the brushless motor is a stepper type motor.
3. A system according to claim 1, wherein the regulator means delivers a signal (SAT) to the processor means, said signal corresponding to the phase offset of the current injected into the plurality of stator windings, thereby enabling the delay between the real current and the reference therefor to be corrected.
4. The system according to claim 1, wherein the indicator device further comprises a second series of indications of the mechanical position of the rotor, of number greater than the number of indications in the first series.
5. The system according to claim 1, wherein the indicator device comprises a disk in which each series of indications is formed by a plurality of steps of marks suitable for being detected by the optical detector device, said plurality of marks being disposed uniformly in a circular band around the shaft of the disk.
6. The system according to claim 5, wherein the disk comprises a first plurality of fifty sets of marks disposed in a first circular band and corresponding to fifty electrical cycles of the motor.
7. The system according to claim 6, wherein the disk further comprises a second plurality of 500 sets of marks uniformly disposed in a second circular band adjacent to the first band.
8. The system according to claim 1, including a second processor means connected to said first processor means and including means for generating motor speed profiles and external connection means.
9. A system according to claim 1, wherein the or each processor means are constituted by a microprocessor.
10. The system according to claim 1, wherein the or each processor means are constituted by a dedicated integrated circuit.
11. The system according to claim 1, wherein the processor means includes means for storing an offset between the position of the indicator device and the mechanical position of the rotor.
12. The system according to claim 11, wherein the processor means synchronizes each electrical cycle automatically on the mechanical position of the rotor while taking account of the stored offset.
13. The system according to claim 1, wherein the processor means operates either by tracking speed profile, or by tracking the mechanical position of the rotor in order to avoid loss of synchronization, with switchover between the two modes being implemented automatically.
14. A control system for a brushless motor or stepping motor comprising a rotor mounted on a shaft and a stator having a plurality of phase windings powered electrically in a predetermined electrical cycle to cause the rotor to advance, said system comprising:
an indicator device for indicating the mechanical position of the rotor and placed on the shaft thereof;
an optical detector device for measuring the mechanical position of the rotor from the indicator device, and co-operating therewith to form an incremental coder device for the mechanical position of the rotor; and
a motor control assembly comprising processor means for processing signals encoding the mechanical position of the rotor connected to regulator means for regulating the power supply to the plurality of stator windings;
wherein the indicator device comprises a first series of indications arranged in a pattern of periodicity that corresponds to a period of an electrical cycle of the motor so as to provide an indication on the phase of the electrical cycle of the stator based on the movement of the rotor, and a second series of indications arranged in a pattern providing an indication of the position of the rotor;
wherein the incremental coder device delivers a synchronizing signal to the processor means, the processing means synchronizing the start of an electrical cycle based on the mechanical position of the rotor for all electrical cycles.
15. The system according to claim 14, wherein the disk further comprises a second plurality of 500 sets of marks uniformly disposed in a second circular band adjacent to the first band.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-23. (canceled)
24. A memory cell providing reading, writing, and storage of a data bit, said cell comprising:
a first transistor that enables reading and writing of said data bit; and
a second transistor that enables storage of said data bit, wherein said first transistor is electrically connected to said second transistor.
25. The memory cell of claim 24 further comprising:
said first transistor having a first source node, a first gate node, and a first drain node; and
said second transistor having a second drain node that is electrically connected to said first drain node, a second source node, and a second gate node.
26. The memory cell of claim 25 wherein said second source node is electrically floating.
27. The memory cell of claim 25 wherein said second gate node is connected to a bias voltage level.
28. The memory cell of claim 25 wherein said first drain node and said second drain node, connected together, constitute a storage node.
29. The memory cell of claim 25 further comprising a pulsed voltage driver connected to said second gate node.
30. The memory cell of claim 25 wherein said first gate node comprises a memory readwrite-enable line.
31. The memory cell of claim 25 wherein said first source node comprises a memory bit line that is written to and read from.
32. The memory cell of claim 24 wherein said first transistor is a field-effect-transistor (FET).
33. The memory cell of claim 24 wherein said second transistor is a FET.
34. The memory cell of claim 24 wherein said second transistor has a first storage capacitance associated with a junction of said second transistor.
35. The memory cell of claim 24 wherein said second transistor has a second storage capacitance associated with an oxide layer of said second source node to store said data bit.
36. A method for reducing leakage current when storing a data bit in an embedded memory cell, said method comprising:
writing a data bit to a memory cell during a first time segment;
applying a transistor disabling reference ground potential to a first transistor of said memory cell during a second time segment;
applying a first reference voltage to said first transistor during said second time segment; and
applying a second reference voltage to a second transistor during at least a portion of said second time segment.
37. The method of claim 36 wherein said transistor disabling reference ground potential is applied to a first gate node of said first transistor.
38. The method of claim 36 wherein said first reference voltage is applied to a first source node of said first transistor.
39. The method of claim 36 wherein said second reference voltage is applied to a second gate node of said second transistor.
40. The method of claim 36 wherein said second time segment is after said first time segment.
41. The method of claim 36 wherein said writing comprises:
applying a first voltage to said first source node of said first transistor during said first time segment;
applying a second voltage level, with respect to said reference ground potential, to said first gate node of said first transistor during said first time segment; and
applying said second voltage level to said second gate node of said second transistor during at least said first time segment.
42. The method of claim 41 wherein said first voltage is a data bit voltage.
43. The method of claim 41 wherein said second voltage level is a readwrite enabling voltage.
44. The method of claim 41 wherein said second voltage level is equal to said first reference voltage.
45. The method of claim 41 wherein said second voltage level is more positive than said first reference voltage.
46. The method of claim 36 wherein said second reference voltage is more positive than said first reference voltage.
47. The method of claim 36 wherein a first drain node of said first transistor is electrically connected to a second drain node of said second transistor.
48. The method of claim 36 wherein a second source node of said second transistor is electrically floating.
49. The method of claim 36 wherein said first transistor is a FET.
50. The method of claim 36 wherein said second transistor is a FET.
51. The method of claim 36 wherein said second transistor has a first storage capacitance associated with a junction of said second transistor.
52. The method of claim 36 wherein said second transistor has a second storage capacitance associated with an oxide layer of a second source node of said second transistor to store said data bit.
53. The method of claim 36 wherein said data bit is represented by a voltage level corresponding to said reference ground potential.
54. The method of claim 36 wherein said data bit is represented by a voltage level that is more positive than said reference ground potential.