1. An ESD protection circuit, comprising:
a VDD bus;
a VSS bus;
an IC pad;
a PMOS transistor coupled to the IC pad and the VDD bus, and having a plurality of gate fingers, a plurality of source contacts, and a plurality of drain contacts;
an NMOS transistor coupled to the IC pad and the VSS bus, and having a plurality of gate fingers, a plurality of source contacts, and a plurality of drain contacts;
wherein the pitch of the PMOS is smaller than the pitch of the NMOS, with the pitch being defined as the distance between the center of a drain contact and the center of an adjacent source contact for the particular transistor; and
wherein each gate finger has a length, and wherein the length of the gate fingers of the NMOS is greater than the length of the gate fingers of the PMOS.
2. The circuit of claim 1, wherein the pitch of the PMOS is less than 80% of the pitch of the NMOS.
3. The circuit of claim 1, wherein the pitch of the PMOS is less than or equal to 50% of the pitch of the NMOS.
4. The circuit of claim 1, wherein the gate fingers of the NMOS and the PMOS are parallel to each other.
5. The circuit of claim 1, wherein the NMOS has a gate finger, and the PMOS has a gate finger, with the gate finger of the NMOS and the gate finger of the PMOS being misaligned with respect to each other.
6. The circuit of claim 1, wherein the length of the gate fingers of the PMOS is less than 60% of the length of the gate fingers of the NMOS.
7. The circuit of claim 1, further including a bond pad, with the NMOS and the PMOS coupled to the same side of the bond pad.
8. The circuit of claim 1, wherein the NMOS and the PMOS each has a drain region, and further including a plurality of islands provided in the drain region of the NMOS.
9. The circuit of claim 8, wherein the drain region of the PMOS is devoid of islands.
10. The circuit of claim 1, further including a resistor which is coupled between a gate finger of the NMOS and the VSS power bus.
11. The circuit of claim 1, further including a capacitor which is coupled to a gate finger of the NMOS and the IC pad.
12. An inputoutput circuit, comprising:
an IC pad;
a PMOS transistor directly connected to the IC pad and gate signals, and having a plurality of gate fingers, a plurality of drain contacts and a plurality of source contacts; and
an NMOS transistor directly connected to the IC pad and gate signals, and having a plurality of gate fingers, a plurality of drain contacts and a plurality of source contacts;
wherein the pitch of the PMOS is smaller than the pitch of the NMOS, with the pitch being defined as the distance between the center of a drain contact and the center of an adjacent source contact for the particular transistor.
13. An electrical circuit, comprising:
a PMOS transistor having a plurality of gate fingers, the PMOS transistor having a drain contact and a source contact;
an NMOS transistor having a plurality of gate fingers, the NMOS transistor having a drain contact and a source contact;
wherein the spacing between the drain contact and an adjacent one of the gate fingers (DCGS) for the PMOS is smaller than the DCGS for the NMOS; and
wherein each gate finger has a length, and wherein the length of the gate fingers of the NMOS is greater than the length of the gate fingers of the PMOS.
14. The circuit of claim 13, wherein the DCGS for the PMOS is less than 81% of the DCGS for the NMOS.
15. The circuit of claim 13, wherein the DCGS for the PMOS is less than or equal to 51% of the DCGS for the NMOS.
16. The circuit of claim 13, wherein the NMOS DCGS is 5 um and the PMOS DCGS ranges from 1.5 um to 2.5 um.
17. The circuit of claim 13, wherein the PMOS has twice the number of gate fingers as the NMOS.
18. The circuit of claim 13, wherein the gate fingers of the NMOS and the PMOS are parallel to each other.
19. The circuit of claim 13, wherein the NMOS has a gate finger, and the PMOS has a gate finger, with the gate finger of the NMOS and the gate finger of the PMOS being misaligned with respect to each other.
20. The circuit of claim 13, wherein the length of the gate fingers of the PMOS is less than 61% of the length of the gate fingers of the NMOS.
21. The circuit of claim 13, further including a bond pad, with the NMOS and the PMOS coupled to the same side of the bond pad.
22. The circuit of claim 13, further including a plurality of islands provided in the drain region of the NMOS.
23. The circuit of claim 22, wherein the drain region of the PMOS is devoid of islands.
24. The circuit of claim 13, further including a resistor which is coupled between a gate finger of the NMOS and a VSS power bus.
25. The circuit of claim 13, further including a capacitor which is coupled to a gate finger of the NMOS and an IC pad.
26. The circuit of claim 13, wherein the spacing between the source contact and the gate (SCGS) for the PMOS is smaller than the SCGS for the NMOS.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fiber-fortified chocolate comprising:
chocolate;
cocoa;
cocoa butter;
a sweetener;
an emulsifier; and,
between about 3 to about 9 percent by weight wheat dextrin.
2. A fiber-fortified chocolate as recited in claim 1 wherein the sweetener is sugar.
3. A fiber-fortified chocolate as recited in claim 1 wherein the sweetener is an artificial sweetener.
4. A fiber-fortified chocolate as recited in claim 3 wherein the artificial sweetener comprises sucralose.
5. A fiber-fortified chocolate as recited in claim 3 wherein the artificial sweetener comprises polydextrose.
6. A fiber-fortified chocolate as recited in claim 1 wherein the sweetener comprises corn syrup.
7. A fiber-fortified chocolate as recited in claim 1 wherein the emulsifier comprises soy lecithin.
8. A fiber-fortified chocolate as recited in claim 1 wherein the emulsifier comprises carrageenan.
9. A fiber-fortified chocolate as recited in claim 1 wherein the emulsifier comprises mono- andor di-glycerides.
10. A fiber-fortified chocolate as recited in claim 1 wherein the emulsifier comprises xanthan gum.
11. A fiber-fortified chocolate as recited in claim 1 wherein the emulsifier comprises polyglycerol polyricinoleate (PGPR).
12. A fiber-fortified chocolate as recited in claim 1 wherein the emulsifier comprises Di-Acetyl Tartaric (acid) Ester of Monoglyceride (DATEM).
13. A fiber-fortified chocolate as recited in claim 1 further comprising soy protein.
14. A fiber-fortified chocolate as recited in claim 1 further comprising egg protein.
15. A fiber-fortified chocolate as recited in claim 1 further comprising corn starch.
16. A fiber-fortified chocolate as recited in claim 1 further comprising non-fat dry milk.
17. A fiber-fortified chocolate consisting essentially of:
chocolate;
cocoa;
cocoa butter;
a sweetener;
an emulsifier; and,
between about 3 to about 9 percent by weight wheat dextrin.
18. A fiber-fortified chocolate as recited in claim 17 wherein the sweetener is sugar.
19. A fiber-fortified chocolate as recited in claim 17 wherein the sweetener is an artificial sweetener selected from the group consisting of sucralose, polydextrose and sugar alcohols.
20. A fiber-fortified chocolate as recited in claim 17 wherein the emulsifier is selected from the group consisting of soy lecithin, carrageenan, mono- andor di-glycerides, xanthan gum, polyglycerol polyricinoleate (PGPR) and the Di-Acetyl Tartaric (acid) Ester of Monoglyceride (DATEM).
21. A food product comprising:
a first substrate having a first water activity;
a second substrate having a second water activity greater than the first water activity; and,
a layer of chocolate separating the first substrate from the second substrate, the layer having a thickness sufficient to substantially prevent the migration of water from the second substrate to the first substrate.
22. A food product as recited in claim 21 wherein the chocolate layer consists essentially of chocolate, cocoa, cocoa butter, a sweetener, an emulsifier and between about 3 to about 9 percent by weight wheat dextrin.
23. A method for making a multi-layer confection comprising:
coating the interior of a mold having an interior cavity with chocolate;
placing a first substrate having a first water activity in the mold;
covering the first substrate with a first layer of chocolate having sufficient thickness to substantially prevent the migration of water through the layer;
sealing the perimeter of the layer of chocolate to the chocolate coating the interior of the mold;
placing a second substrate having a second water activity different from the first water activity into the mold;
covering the second substrate with a second layer of chocolate; and
sealing the perimeter of the second layer of chocolate to the chocolate coating the interior of the mold.
24. A method as recited in claim 23 wherein sealing the perimeter of the layer of chocolate comprises adding melted chocolate to the mold such that the melted chocolate contacts the chocolate coating the interior of the mold.
25. A method as recited in claim 23 wherein the first layer of chocolate comprises wheat dextrin.
26. A method as recited in claim 25 wherein the wheat dextrin comprises between about 3 to about 9 percent by weight of the chocolate.
27. A method as recited in claim 23 wherein the first layer of chocolate consists essentially of chocolate, cocoa, cocoa butter, a sweetener, an emulsifier and between about 3 to about 9 percent by weight wheat dextrin.