1. A memory controller comprising:
an output driver to output a first data signal onto a data line; and
termination control circuitry to output termination control signals to a plurality of integrated circuit memory devices, the termination control signals to control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal, wherein the termination control signals specify coupling a termination element having an impedance indicated by a first termination value to the data line within one of the plurality of integrated circuit memory devices selected to receive the first data signal, and wherein the termination control signals further specify coupling a termination element having an impedance indicated by a second termination value to the data line within at least one other of the plurality of integrated circuit memory devices.
2. The memory controller of claim 1 further comprising an interface to output the first and second termination values to the plurality of integrated circuit memory devices.
3. The memory controller of claim 2 wherein the interface to output first and second termination values to the plurality of integrated circuit memory devices is further to output one or more register-programming commands to the plurality of integrated circuit memory devices, the one or more register-programming commands instructing each integrated circuit memory device of the plurality of integrated circuit memory devices to store the first and second termination values in at least one register of the integrated circuit memory device.
4. The memory controller of claim 2 wherein the interface to output first and second termination values to the plurality of integrated circuit memory devices is further to output memory access commands to the plurality of integrated circuit memory devices, each of the memory access commands indicating a memory access operation to be carried out within at least one of the plurality of integrated circuit memory devices.
5. The memory controller of claim 2 wherein the first and second termination values comprise first and second digital codes that are representative of respective impedance selections available within the plurality of integrated circuit memory devices.
6. The memory controller of claim 1 further comprising a plurality of chip-select outputs to output respective chip-select signals to the plurality of integrated circuit memory devices, the chip-select signals indicating which of the plurality of integrated circuit memory devices is selected to receive the first data signal.
7. The memory controller of claim 1 further comprising additional output drivers to output additional data signals to the plurality of integrated circuit memory devices in parallel with the first data signal.
8. A memory controller comprising:
an interface to output first and second digital values to set impedances of first and second load elements, respectively, within an integrated circuit memory device;
an output driver to output a first data signal to the integrated circuit memory device via a data line;
a first control output to output a first termination control signal to a first switch element within the integrated circuit memory device, the first switch element switchably coupling the data line to the first load element or decoupling the data line from the first load element according to the state of the first termination control signal; and
a second control output to output a second termination control signal to a second switch element within the integrated circuit memory device, the second switch element switchably coupling the data line to the second load element or decoupling the data line from the second load element according to the state of the second termination control signal.
9. The memory controller of claim 8 wherein the interface to output first and second digital values to the integrated circuit memory device is further to output one or more register-programming commands instructing the integrated circuit memory device to store the first and second digital values in at least one register of the integrated circuit memory device.
10. The memory controller of claim 8 wherein the interface to output first and second digital values to the integrated circuit memory device is further to output memory access commands to the integrated circuit memory device, each memory access command indicating a memory access operation to be carried out within the integrated circuit memory device.
11. The memory controller of claim 8 wherein the first and second digital values comprise first and second digital codes that are representative of respective impedance settings available within the integrated circuit memory device.
12. The memory controller of claim 8 further comprising a first chip-select output to output a chip-select signal via a chip-select line coupled to the integrated circuit memory device to indicate that information output via the interface, including the first and second digital values, is to be received by the integrated circuit memory device.
13. The memory controller of claim 8 further comprising additional output drivers to output additional data signals to the integrated circuit memory device in parallel with the first data signal.
14. The memory controller of claim 8 further comprising termination control circuitry to enable the first and second control outputs to output the first and second termination control signals in respective states according to whether the integrated circuit memory device is selected to receive the first data signal.
15. The memory controller of claim 14 wherein the termination control circuitry is configured to enable the first and second control outputs to output the first and second termination control signals in states that switchably couple the first load element to the data line and switchably decouple the second load element from the data line if the integrated circuit memory device is selected to receive the first data signal, and to output the first and second termination control signals in states that switchably decouple the first load element from the data line and switchably couple the second load element to the data line if the integrated circuit memory device is not selected to receive the first data signal.
16. A method of operation within a memory controller, the method comprising:
outputting a first data signal onto an external data line;
outputting termination control to control coupling and decoupling of termination elements to the data line according to which integrated circuit memory device of a plurality of memory integrated circuit memory devices is selected to receive the first data signal, wherein the termination control signals specify coupling a termination element having a first impedance to the data line within one of the plurality of integrated circuit memory devices selected to receive the first data signal, and wherein the termination control signals further specify coupling a termination element having a second impedance to the data line within at least one other of the plurality of integrated circuit memory devices.
17. The method of claim 16 further comprising outputting first and second termination values to the plurality of integrated circuit memory devices via a first interface, the first termination value specifying the first impedance and the second termination value specifying the second impedance.
18. The method of claim 17 further comprising outputting one or more register-programming commands to the plurality of integrated circuit memory devices via the first interface, the one or more register-programming commands instructing each integrated circuit memory device of the plurality of integrated circuit memory devices to store the first and second termination values in at least one register of the integrated circuit memory device.
19. The method of claim 17 further comprising outputting memory access commands to the plurality of integrated circuit memory devices via the first interface, each of the memory access commands indicating a memory access operation to be carried out within at least one of the plurality of integrated circuit memory devices.
20. The method of claim 17 wherein outputting the first and second termination values comprises outputting first and second digital codes that are representative of respective impedance selections available within the plurality of integrated circuit memory devices.
21. The method of claim 16 further comprising outputting a plurality of chip-select signals to the plurality of integrated circuit memory devices via respective chip-select lines, the plurality of chip-select signals indicating which of the plurality of integrated circuit memory devices is selected to receive the first data signal.
22. A method of operation within a memory controller, the method comprising:
outputting first and second digital control values to an integrated circuit memory device via a first interface, the first digital control value to set an impedance of a first load element within the integrated circuit memory device and the second digital control value to set an impedance of a second load element within the integrated circuit memory device;
outputting a first data signal to the integrated circuit memory device via a data line;
outputting a first termination control signal to a first switch element within the integrated circuit memory device, the first switch element switchably coupling the data line to the first load element or decoupling the data line from the first load element according to the state of the first termination control signal; and
outputting a second termination control signal to a second switch element within the integrated circuit memory device, the second switch element switchably coupling the data line to the second load element or decoupling the data line from the second load element according to the state of the second termination control signal.
23. The method of claim 22 further comprising outputting one or more register-programming commands to the integrated circuit memory device via the first interface, the one or more register-programming commands instructing the integrated circuit memory device to store the first and second digital values in at least one register of the integrated circuit memory device.
24. The method of claim 22 further comprising outputting memory access commands to the integrated circuit memory device via the first interface, each memory access command indicating a memory access operation to be carried out within the integrated circuit memory device.
25. The method of claim 22 wherein the first and second digital values comprise first and second digital codes that are representative of respective impedance settings available within the integrated circuit memory device.
26. The method of claim 22 further comprising outputting a chip-select signal to the integrated circuit memory device via a chip-select line, the chip-select signal indicating that information output via the first interface, including the first and second digital values, is to be received by the integrated circuit memory device.
27. The method of claim 22 wherein outputting the first and second termination control signals comprises outputting the first and second termination control signals in respective states according to whether the integrated circuit memory device is selected to receive the first data signal.
28. The method of claim 27 wherein outputting the first and second termination control signals in respective states according to whether the integrated circuit memory device is selected to receive the first data signal comprises outputting the first and second termination control signals in states that switchably couple the first load element to the data line and switchably decouple the second load element from the data line if the integrated circuit memory device is selected to receive the first data signal, and outputting the first and second termination control signals in states that switchably decouple the first load element from the data line and switchably couple the second load element to the data line if the integrated circuit memory device is not selected to receive the first data signal.
29. A memory controller comprising termination control circuitry to generate termination control signals that control coupling and decoupling of termination elements to an external data line according to which memory device of a plurality of integrated circuit memory devices is selected to receive a first data signal, wherein:
the termination control signals specify coupling a termination element having an impedance first termination value to the data line within one of the plurality of integrated circuit memory devices is selected to receive the first data signal via the external data line; and
the termination control signals specify coupling a termination element having an impedance indicated by the second termination value to the external data line within at least one other memory device of the plurality of integrated circuit memory devices.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An intervertebral fusion with fixation device configured to be implanted between plural vertebrae, the device comprising:
a spacer with an insertion wall, a trailing wall opposite to the insertion wall, a first lateral wall, a second lateral wall opposite to the first lateral wall, a top surface, and a bottom surface opposite to the top surface, the top and bottom surfaces each extending between the insertion wall and the trailing wall for contact with first and second vertebra respectively, wherein a first hole and a second hole extends through the spacer from the trailing wall toward the top and bottom surfaces respectively;
a first cannulated bone screw including a first tip at a first leading end and a first head at an opposed first trailing end, the first leading end rigidly maintaining the first cannulated bone screw in a first preloaded position in the first hole along a first linear trajectory through threaded engagement of the first leading end inside the first hole, when in the first preloaded position the first tip not extending substantially above the top surface and the first head being spaced away from the spacer, the first cannulated bone screw configured to penetrate and secure to the first vertebra by advancing along the first linear trajectory to a first locked position in which the first head is advanced into the first hole; through direct engagement with a driving element and
a second cannulated bone screw including a second tip at a second leading end and a second head at an opposed second trailing end, the second leading end rigidly maintaining the second cannulated bone screw in a second preloaded position in the second hole along a second linear trajectory that is different and divergent from the first linear trajectory through threaded engagement of the second leading end inside the second hole, when in the second preloaded position the second tip not extending substantially below the bottom surface and the second head being spaced away from the spacer, the second cannulated bone screw configured to penetrate and secure to the second vertebra by advancing along the second trajectory to a second locked position in which the second head is advanced into the second hole through direct engagement with the driving element.
2. The intervertebral fusion with fixation device of claim 1, wherein the spacer includes a through opening having an entrance proximate the top surface and an exit proximate the bottom surface to facilitate contact and in-growth of bone fusion material with the first vertebra and the second vertebra, wherein at least one of the first hole and the second hole extends to the through opening.
3. The intervertebral fusion with fixation device of claim 1, wherein the spacer is made of polyetheretherketone (PEEK), other polymers, metal, ceramics, or composites.
4. The intervertebral fusion with fixation device of claim 1, wherein the first head includes a recess for matingly receiving the driving element therein and limiting advancement of the driving element along the first trajectory.
5. The intervertebral fusion with fixation device of claim 1, wherein the first head includes a protrusion configured to penetrate and lock into the first hole to prevent screw toggling and extrusion.
6. The intervertebral fusion with fixation device of claim 1, wherein the spacer includes ridges protruding from at least one of the top surface and the bottom surface providing reinforcing structure for the first hole and the second hole.
7. The intervertebral fusion with fixation device of claim 1, wherein the first cannulated bone screw is maintained in the first preloaded position while the second cannulated bone screw is maintained in the second preloaded position.
8. An intervertebral fusion with fixation system, the system compromising:
an intervertebral fusion with fixation device configured to be implanted between plural vertebrae, the device comprising:
a spacer with an insertion wall, a trailing wall opposite to the insertion wall, a first lateral wall, a second lateral wall opposite to the first lateral wall, a top surface, and a bottom surface opposite to the top surface, the top and bottom surfaces each extending between the insertion wall and the trailing wall for contact with first and second vertebra respectively, wherein a first hole and a second hole extends through the spacer from the trailing wall toward the top and bottom surfaces respectively;
a first cannulated bone screw including a first tip at a first leading end and a first head at an opposed first trailing end, the first leading end rigidly maintaining the first cannulated bone screw in a first preloaded position in the first hole along a first linear trajectory through threaded engagement of the first leading end inside the first hole, when in the first preloaded position the first tip not extending substantially above the top surface and the first head being spaced away from the spacer; and
a second cannulated bone screw including a second tip at a second leading end and a second head at an opposed second trailing end, the second leading end rigidly maintaining the second cannulated bone screw in a second preloaded position in the second hole along a second linear trajectory that is different and divergent from the first linear trajectory through threaded engagement of the second leading end inside the second hole, when in the second preloaded position the second tip not extending substantially below the bottom surface and the second head being spaced away from the spacer, the second cannulated bone screw configured to penetrate and secure to the second vertebra by advancing along the second trajectory to a second locked position in which the second head is advanced into the second hole; and an integrated drill and screwdriver instrument, the instrument comprising:
a drilling element configured to be inserted through a cannula of the first cannulated bone screw to penetrate the first vertebra along the first linear trajectory; and
a driving element from which the drilling element extends, wherein the driving element is configured to engage and rotate the first cannulated bone screw from the first preloaded position into the first vertebra only after the drilling element has penetrated and advanced into the first vertebra, the driving element further rotating the first cannulated bone screw to a first locked position in which the first head is disposed in the first hole.
9. The intervertebral fusion with fixation system of claim 8, wherein the spacer includes a through opening having an entrance proximate the top surface and an exit proximate the bottom surface to facilitate contact and in-growth of bone fusion material with the first vertebra and the second vertebra, wherein at least one of the first hole and the second hole extends to the through opening.
10. The intervertebral fusion with fixation system of claim 8, wherein the first head includes a recess for matingly receiving the driving element therein and limiting advancement of the driving element along the first trajectory.
11. The intervertebral fusion with fixation system of claim 8, wherein the first head including a protrusion configured to penetrate and lock into the first hole to prevent screw toggling and extrusion.
12. The intervertebral fusion with fixation system of claim 8, wherein the threaded engagement of the first leading end cuts into the spacer inside the first hole for rigidly maintaining the first cannulated bone screw in the first preloaded position.
13. The intervertebral fusion with fixation system of claim 8, wherein the first cannulated bone screw is maintained in the first preloaded position while the second cannulated bone screw is maintained in the second preloaded position.