1. (canceled)
2. A semiconductor device comprising:
a frame;
a first image capture element incorporated in the frame; and
an electroluminescence display device incorporated in the frame,
wherein the semiconductor device is configured so that an image captured by the first image capture element is displayed on a first side of the electroluminescence display device,
wherein the electroluminescence display device comprises a pixel which includes:
a transistor;
a first insulating film over the transistor;
a first electrode over the first insulating film;
a second insulating film over the first insulating film, the second insulating film covering an edge portion of the first electrode;
an electroluminescence layer over the first electrode and the second insulating film; and
a second electrode over the electroluminescence layer; and
wherein part of the second insulating film overlaps with the edge portion and has a taper shape.
3. The semiconductor device according to claim 2,
wherein the first image capture element is configured to capture an image on a second side of the electroluminescence display device, and
wherein the second side is opposite to the first side with respect to the electroluminescence display device.
4. The semiconductor device according to claim 2, further comprising a second image capture element,
wherein the semiconductor device is configured to capture an image on the first side.
5. The semiconductor device according to claim 2,
wherein the semiconductor device is configured so as to be combined with a headphone.
6. The semiconductor device according to claim 2,
wherein the semiconductor device is configured so as to be combined with a headphone and to receive electric wave.
7. The semiconductor device according to claim 2, further comprising a speaker.
8. The semiconductor device according to claim 2,
wherein the first electrode and the second electrode are configured so that light emitted from the electroluminescence layer is extracted through the second electrode.
9. The semiconductor device according to claim 2,
wherein the first electrode overlaps with the transistor.
10. The semiconductor device according to claim 2,
wherein the transistor has a plurality of gate electrodes.
11. The semiconductor device according to claim 2,
wherein the pixel further comprises a second transistor to which a gate of the transistor is electrically connected,
wherein the second transistor has a plurality of gate electrodes.
12. The semiconductor device according to claim 2,
wherein the pixel further comprises:
a first line and a second line which are arranged to be parallel to each other; and
a second transistor,
wherein the first line is electrically connected to a gate of the second transistor, and
wherein the second line is configured to supply current to the first electrode through the transistor.
13. The semiconductor device according to claim 2,
wherein the pixel further comprises:
a first line and a second line which are arranged to be perpendicular to each other; and
a second transistor,
wherein the first line is electrically connected to a gate of the second transistor, and
wherein the second line is configured to supply current to the first electrode through the transistor.
14. The semiconductor device according to claim 13,
wherein the first line and the second line are shared by the pixel and a second pixel adjacent to the pixel.
15. The semiconductor device according to claim 2,
wherein the frame is configured so that the semiconductor device is placed in front of an eye of a user.
16. The semiconductor device according to claim 2, further comprising a first substrate and a second substrate,
wherein the electroluminescence display device is interposed between the first substrate and the second substrate,
wherein the first substrate and the second substrate are bonded to each other with a first sealing material and a second sealing material,
wherein the pixel is surrounded by the first sealing material, and
wherein the second sealing material is located outside the first sealing material.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A bandpass delta sigma truncator comprising:
input means for receiving a series of first multi-bit digital signals each having:
(a) a number of data bits, and
(b) a first number of sign bits;
sign extending means for sign extending each of the first multi-bit digital signals to a second multi-bit digital signal having:
(a) the same number of data bits as the number of data bits in the first multi-bit digital signals, and
(b) a second number of sign bits;
output means for supplying from a series of third multi-bit digital signals each individually associated with one of the second multi-bit digital signals and each having the same number of data bits as in an associated second multi-bit digital signal:
(a) a series of fourth multi-bit digital signals each having a selected number of the most significant data bits of the third multi-bit digital signals, and
(b) a series of fifth multi-bit digital signals each having the remaining number of the least significant data bits of the third multi-bit digital signals;
means for:
(a) delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals, and
(b) delaying by a period of time equal to twice the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals and inverting the fifth multi-bit digital signals that have been delayed by a period of time equal to twice the time between successive first multi-bit digital signals;
means for multiplying by a multiplier number related to the ratio of a selected frequency to the frequency of the first multi-bit digital signals each of the fifth multi-bit digital signals delayed by a period of time equal to the time between successive first multi-bit digital signals and developing a series of sixth multi-bit digital signals having a number of data bits that is the product of the multiplier number and the number of data bits in the fifth multi-bit digital signals; and
summing means for adding to each second multi-bit digital signal:
(a) a fifth multi-bit digital signal that has been delayed by a period of time equal to twice the time between successive first multi-bit digital signals and inverted, and
(b) a sixth multi-bit digital signal to develop the series of third multi-bit digital signals.
2. A bandpass delta sigma truncator according to claim 1 wherein:
(a) each first multi-bit digital signal is a ten bit digital signal having nine data bits and one sign bit,
(b) each second multi-bit digital signal is an eleven bit digital signal having nine data bits and two sign bits,
(c) each third multi-bit digital signal is a nine bit digital signal having nine data bits,
(d) each fourth multi-bit digital signal is a six bit digital signal having six data bits,
(e) each fifth multi-bit digital signal is a three bit digital signal having three data bits,
(f) each sixth multi-bit digital signal is a four bit digital signal having four data bits,
(g) the multiplier number is 1.75,
(h) the selected frequency is 5 MHZ, and
(i) the frequency of the first multi-bit digital signals is 30 MHZ.
3. A bandpass delta sigma truncator according to claim 1 further including means between said summing means and said output means for determining whether the value of any third multi-bit digital signal is one of:
(a) greater than a first value, and
(b) less than a second value.
4. A bandpass delta sigma truncator according to claim 2 further including means between said summing means and said output means for determining whether the value of any third multi-bit digital signal is one of:
(a) greater than a first value, and
(b) less than a second value.
5. A bandpass delta sigma truncator according to claim 2 wherein said means for delaying and inverting the fifth multi-bit digital signals include:
(a) a digital delay circuit for delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals, and
(b) a digital delay and inverter circuit for:
(1) additionally delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals delayed by said digital delay circuit, and
(2) inverting the additionally delayed fifth multi-bit digital signals.
6. A bandpass delta sigma truncator according to claim 4 wherein said means for delaying and inverting the fifth multi-bit digital signals include:
(a) a digital delay circuit for delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals, and
(b) a digital delay and inverter circuit for:
(1) additionally delaying by a period of time equal to the time between successive first multi-bit digital signals each of the fifth multi-bit digital signals delayed by said digital delay circuit, and
(2) inverting the additionally delayed fifth multi-bit digital signals.
7. A method for truncating a multi-bit digital signal comprising the steps of:
providing a series of first multi-bit digital signals each having:
(a) a number of data bits, and
(b) a first number of sign bits;
sign extending each of the first multi-bit digital signals to a second multi-bit digital signal having:
(a) the same number of data bits as the number of data bits in the first multi-bit digital signals, and
(b) a second number of sign bits;
adding to each second multi-bit digital signal to develop a series of third multi-bit digital signals each individually associated with one of the second multi-bit digital signals and each having the same number of data bits as in an associated second multi-bit digital signal:
(a) a multi-bit digital signal that has been:
(1) developed from a selected number of the least significant bits of the third multi-bit digital signals, and
(2) delayed by a period of time equal to twice the time between successive first multi-bit digital signals and inverted, and
(b) a multi-bit digital signal that has been:
(1) developed from the selected number of the least significant bits of the third multi-bit digital signals, and
(2) delayed by a period of time equal to the time between successive first multi-bit digital signals and multiplied by a multiplier number related to the ratio of a selected frequency to the frequency of the first multi-bit digital signals; and
developing from the third multi-bit digital signals a series of fourth digital signals each having a selected number of the most significant data bits of the third multi-bit digital signals.
8. A method for truncating a multi-bit digital signal according to claim 7 wherein:
(a) each first multi-bit digital signal is a ten bit digital signal having nine data bits and one sign bit,
(b) each second multi-bit digital signal is an eleven bit digital signal having nine data bits and two sign bits,
(c) each third multi-bit digital signal is a nine bit digital signal having nine data bits,
(d) each fourth multi-bit digital signal is a six bit digital signal having six data bits,
(e) each multi-bit digital signal that has been delayed by a period of time equal to twice the time between successive first multi-bit digital signals and inverted is a three bit digital signal having three data bits,
(f) each multi-bit digital signal delayed by a period of time equal to the time between successive first multi-bit digital signals and multiplied by a multiplier number related to the ratio of a selected frequency to the frequency of the first multi-bit digital signals is a four bit digital signal having four data bits,
(g) the multiplier number is 1.75,
(h) the selected frequency is 5 MHZ, and
(i) the frequency of the first multi-bit digital signals is 30 MHZ.
9. A method for truncating a multi-bit digital signal according to claim 7 further including the step of determining whether the value of any third multi-bit digital signal is one of:
(a) greater than a first value, and
(b) less than a second value.
10. A method for truncating a multi-bit digital signal according to claim 8 further including the step of determining whether the value of any third multi-bit digital signal is one of:
(a) greater than a first value, and
(b) less than a second value.