1. A system comprising:
a multi-core computer processor;
wherein one or more cores of the multi-core computer processor are configured as a security co-processor for the system and for other cores of the multi-core processor;
wherein an operating system of the security co-processor is independent of operating systems of the other cores of the multi-core processor;
wherein the security co-processor is configured to boot before the other cores and to enforce security policy on the other cores;
wherein the security co-processor is configured to enforce one or more privilege levels including an untrusted level, a user level, a supervisor level, and a maintenance level;
wherein the untrusted level comprises processing downloaded software code from a party other than an administrator of the system;
wherein the user level comprises processing software code and data from a source approved by the administrator of the system;
wherein the supervisor level comprises dynamic management of the system including changing operating system settings and changing hardware settings; and
wherein the maintenance level comprises changes that affect the security of the system including processing kernel updates, updating keys for authentication, and privileged operations.
2. The system of claim 1, wherein the security co-processor comprises a single core.
3. The system of claim 1, wherein the security co-processor comprises a distributed firewall.
4. The system of claim 1, wherein the security co-processor is configured to control access control hardware including a memory management unit.
5. The system of claim 1, wherein the untrusted level comprises a limited access to random access memory and no write access to certain files.
6. The system of claim 1, wherein the system comprises one of more of a control system for an industrial process, a supervisory control and data acquisition process (SCADA), a system for a building control process, and a control system for an aircraft.
7. The system of claim 1, wherein the security co-processor is configured to handle device input and device output in the system.
8. A system comprising:
a multi-core computer processor;
wherein one or more cores of the multi-core computer processor are configured as a safety manager co-processor for the system and for other cores of the multi-core processor;
wherein an operating system of the safety manager co-processor is independent of operating systems of the other cores of the multi-core processor;
wherein the safety manager co-processor is configured to boot before the other cores and to enforce safety policy on the other cores;
wherein the safety manager co-processor is configured to enforce one or more privilege levels including an untrusted level, a user level, a supervisor level, and a maintenance level;
wherein the untrusted level comprises processing downloaded software code from a party other than an administrator of the system;
wherein the user level comprises processing software code and data from a source approved by the administrator of the system;
wherein the supervisor level comprises dynamic management of the system including changing operating system settings and changing hardware settings; and
wherein the maintenance level comprises changes that affect the security of the system including processing kernel updates, updating keys for authentication, and privileged operations.
9. The system of claim 8, wherein the safety manager co-processor comprises a single core.
10. The system of claim 8, wherein the safety manager co-processor is configured to control access control hardware including a memory management unit.
11. The system of claim 8, wherein the system comprises one or more of a control system for an industrial process, a supervisory control and data acquisition process (SCADA), a system for a building control process, and a control system for an aircraft.
12. The system of claim 1, wherein the safety manager co-processor is configured to handle device input and device output in the system.
13. A system comprising:
a multi-core computer processor;
wherein one or more cores of the multi-core computer processor are configured as a security co-processor for the system and for other cores of the multi-core processor;
wherein one or more cores of the multi-core computer processor are configured as a safety manager co-processor for the system and for other cores of the multi-core processor;
wherein one or more of an operating system of the security co-processor and an operating system of the safety manager co-processor are independent of operating systems of the other cores of the multi-core processor;
wherein one or more of the security co-processor and the safety manager co-processor are configured to boot before the other cores and to enforce one or more of security policy and safety policy on the other cores;
wherein one or more of the security co-processor and the safety manage processor are configured to enforce one or more privilege levels including an untrusted level, a user level, a supervisor level, and a maintenance level;
wherein the untrusted level comprises processing downloaded software code from a party other than an administrator of the system;
wherein the user level comprises processing software code and data from a source approved by the administrator of the system;
wherein the supervisor level comprises dynamic management of the system including changing operating system settings and changing hardware setting; and
wherein the maintenance level comprises changes that affect the security of the system including processing kernel updates, updating keys for authentication, and privileged operations.
14. The system of claim 13, wherein the security co-processor and the safety manager co-processor comprise a single core.
15. The system of claim 13, wherein the security co-processor comprises a distributed firewall.
16. The system of claim 13, wherein one or more of the security co-processor and the safety manager co-processor are configured to control access control hardware including a memory management unit.
17. The system of claim 13, wherein the system comprises one or more of a control system for an industrial process, a supervisory control and data acquisition process (SCADA), a system for a building control process, and a control system for an aircraft.
18. The system of claim 13, wherein one or more of the security co-processor and the safety manager co-processor are configured to handle device input and device output in the system.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An image signal processing apparatus outputting, to a projector, an output image signal to project image light onto a projection plane of an arbitrary shape, the image signal processing apparatus comprising:
an image signal input which receives a two-dimensional image signal to project image light onto a two-dimensional projection plane;
an external input which externally receives
a distortion correction table as a correspondence map between the two-dimensional projection plane and a mesh model of the projection plane of the arbitrary shape, the distortion correction table being used to perform distortion correction processing for the two-dimensional image signal received by the image signal input;
a distortion corrector which performs the distortion correction processing for each pixel of the two-dimensional image signal received by the image signal input with reference to the distortion correction table received by the external input to generate the output image signal to project the image light onto the projection plane; and
an output which outputs the output image signal generated by the distortion corrector to the projector,
wherein the distortion correction table describes at least one shift amount for each pixel of a plurality of pixels for shifting the pixel from a first point before conversion to a second point after the conversion,
the distortion corrector mixes color information of the plurality of pixels before the conversion in a ratio corresponding to the shift amount of each pixel, and
the distortion corrector generates the output image signal with mixed color information of the color information of the plurality of pixels after the conversion of each of the plurality of pixels.
2. The image signal processing apparatus according to claim 1, wherein
the external input inputs a control signal externally controlling an operation of the projector; and
the output outputs the control signal received by the external input to the projector together with the output image signal.
3. The image signal processing apparatus according to claim 1, wherein
the image signal input is configured to simultaneously receive a plurality of two-dimensional image signals, and
the output is configured to simultaneously output a plurality of output image signals, the image signal processing apparatus further comprising:
a signal processor which, upon receiving the plurality of two-dimensional image signals simultaneously received by the image signal input, performs one of processing to make a selection from the plurality of two-dimensional image signals for output through the output and processing to output from the output the output image signal obtained by composing the plurality of two-dimensional image signals.
4. The image signal processing apparatus according to claim 3, further comprising:
a synchronization processor which synchronizes the processing by the signal processor for the plurality of two-dimensional image signals.
5. The image signal processing apparatus according to claim 3, further comprising:
a stereoscopic image disparity two-dimensional image signal generator which generates a disparity image signal using the plurality of two-dimensional image signals received by the image signal input, wherein
the distortion corrector performs the distortion correction processing for the disparity image signal generated by the stereoscopic image disparity two-dimensional image signal generator to generate the output image signal.
6. The image signal processing apparatus according to claim 1, wherein the distortion corrector generates the output image signal by one of a first process and a second process,
the first process including mixing color information of at least two pixels adjacent in an X-axis direction before the conversion according to a position of the representative point of the pixel after the conversion relative to at least the two pixels, and
the second process including mixing color information of at least two pixels adjacent in a Y-axis direction before the conversion according to the position of the representative point of the pixel after the conversion relative to at least the two pixels.
7. The image signal processing apparatus according to claim 1, wherein
the distortion corrector uses a plurality of primary colors as the color information and mixes each of the primary colors of adjacent pixels to generate the output image signal.
8. The image signal processing apparatus according to claim 1, wherein
the distortion corrector uses signals each including brightness information and a color difference signal as the color information and mixes the signals of adjacent pixels to generate the output image signal.
9. The image signal processing apparatus according to claim 1, wherein
the distortion correction table describes a correspondence between the two-dimensional projection plane and the mesh model of the projection plane of the arbitrary shape in an order of input pixels of the two-dimensional image signal, and
upon receiving each of the input pixels described in the distortion correction table, the distortion corrector performs the distortion correction processing using a received pixel.
10. The image signal processing apparatus according to claim 1, wherein
the distortion correction table describes a correspondence between the two-dimensional projection plane and the mesh model of the projection plane of the arbitrary shape in an order of output pixels of the output image signal, and
upon receiving each input pixel described in the distortion correction table, the distortion corrector performs the distortion correction processing using a received pixel and generates the output image signal in an order of the output pixels described in the distortion correction table.
11. A virtual reality creating system, comprising:
a screen including a projection plane of an arbitrary shape with a concave surface faced to a viewer, the screen being capable of displaying an image wider than an effective angle of view of the viewer;
an image signal processor that performs distortion correction used for projecting image light onto the projection plane of the arbitrary shape for a two-dimensional image signal to project image light onto a two-dimensional projection plane and then outputting an output image signal;
an external processor which creates a distortion correction table as a correspondence map between the two-dimensional projection plane and a mesh model of the projection plane of the arbitrary shape; and
a projector which projects an image based on the output image signal outputted from the image signal processor onto the screen, wherein
the image signal processor includes:
an image signal input which receives the two-dimensional image signal;
an external input which receives
a distortion correction table as a correspondence map between the two-dimensional projection plane and a mesh model of the projection plane of the arbitrary shape, the distortion correction table being used to perform the distortion correction processing for the two-dimensional image signal received by the image signal input;
a distortion corrector which performs distortion correction processing for each pixel of the two-dimensional image signal received by the image signal input with reference to the distortion correction table received by the external input to generate the output image signal to project the image light onto the projection plane of the arbitrary shape; and
an output which outputs the output image signal generated by the distortion corrector to the projector,
wherein the distortion correction table describes at least one shift amount for each pixel of a plurality of pixels for shifting the pixel from a first point before conversion to a second point after the conversion,
the distortion corrector mixes color information of the plurality of pixels before the conversion in a ratio corresponding to the shift amount of each pixel, and
the distortion corrector generates the output image signal with mixed color information of the color information of the plurality of pixels after the conversion of each of the plurality of pixels.