1. A method for programming a p-channel MOSFET in a substrate into a reprogrammable switch, the method comprising:
applying a first voltage potential to a source region of the MOSFET;
applying a second voltage potential to a drain region of the MOSFET; and
applying a negative gate potential to a gate region of the MOSFET,
wherein applying the first and second voltage potentials and the negative gate potential causes a hot hole injection from the substrate into a gate oxide of the MOSFET.
2. The method of claim 1, wherein applying the first voltage potential to the source region of the MOSFET comprises grounding the source region of the MOSFET.
3. The method of claim 1, wherein applying the second voltage potential to the drain region of the MOSFET comprises grounding the drain region of the MOSFET.
4. The method of claim 1, wherein applying the negative gate potential to the gate region of the MOSFET comprises applying a sufficiently large negative gate potential to form a conduction channel between the source and drain regions of the MOSFET.
5. The method of claim 1, further comprising operating the MOSFET in a forward direction in a programmed state by:
coupling a sourceline to the source region;
coupling a bitline to the drain region; and
applying a gate potential to the gate region such that a conduction channel is formed between the source region and the drain region.
6. A method for programming a p-channel MOSFET in a substrate into a reprogrammable switch, the method comprising:
coupling a source region of the MOSFET and a drain region of the MOSFET to an electrical ground; and
applying a negative gate potential to a gate region of the MOSFET,
wherein applying the negative gate potential to the gate region causes a hot hole injection from the substrate into a gate oxide of the MOSFET.
7. A method for performing address decoding in a memory, the method comprising:
coupling a plurality of address lines and a plurality of output lines to a programmable decoder having a plurality of rows and a plurality of redundant rows; and
unselecting a row by using hot hole injection to program a programmable switch associated with the row, the programmable switch comprising a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a first sourcedrain region, a second sourcedrain region, a channel region between the first and second sourcedrain regions, and a gate separated from the channel region by a gate oxide,
wherein the MOSFET is a programmed MOSFET having a positive charge trapped in the gate oxide such that a threshold voltage of the MOSFET is significantly altered compared to a threshold voltage of the MOSFET in an unprogrammed state.
8. The method of claim 7, further comprising selecting a redundant row by reprogramming a programmable switch associated with the redundant row, the programmable switch comprising a metal oxide semiconductor field effect transistor (MOSFET) in a substrate, the MOSFET having a first sourcedrain region, a second sourcedrain region, a channel region between the first and second sourcedrain regions, and a gate separated from the channel region by a gate oxide, wherein the programmable switch associated with the redundant row is reprogrammed by removing a trapped positive charge from the gate oxide.
9. The method of claim 7, wherein using hot hole injection to trap the positive charge in the gate oxide comprises:
applying a first voltage potential to a source region of the MOSFET;
applying a second voltage potential to a drain region of the MOSFET; and
applying a negative gate potential to a gate region of the MOSFET,
wherein applying the first and second voltage potentials and the negative gate potential causes a hot hole injection from the substrate into a gate oxide of the MOSFET.
10. The method of claim 9, wherein applying the first voltage potential to the source region of the MOSFET comprises grounding the source region of the MOSFET.
11. The method of claim 9, wherein applying the second voltage potential to the drain region of the MOSFET comprises grounding the drain region of the MOSFET.
12. The method of claim 9, wherein applying the negative gate potential to the gate region of the MOSFET comprises applying a sufficiently large negative gate potential to form a conduction channel between the source and drain regions of the MOSFET.
13. The method of claim 9, further comprising operating the MOSFET in a forward direction in a programmed state by:
coupling a sourceline to the source region;
coupling a bitline to the drain region; and
applying a gate potential to the gate region such that a conduction channel is formed between the source region and the drain region.
14. A method for programming an address decoder in a memory, the method comprising:
writing to a metal oxide semiconductor field effect transistor (MOSFET) associated with a row of the address decoder, thereby causing a positive charge to be trapped in a gate oxide of the MOSFET associated with the row, wherein writing to the MOSFET associated with the row causes the row to be uncoupled from a row driver; and
erasing a MOSFET associated with a redundant row of the address decoder, thereby removing a positive charge trapped in a gate oxide of the MOSFET associated with the redundant row, wherein erasing the MOSFET associated with the redundant row causes the redundant row to be coupled to a redundant row driver.
15. The method of claim 14, wherein writing to the MOSFET associated with the row of the address decoder comprises using hot hole injection to trap the positive charge in the gate oxide of the MOSFET associated with the row of the address decoder.
16. The method of claim 15, wherein using hot hole injection to trap the positive charge in the gate oxide of the MOSFET associated with the row of the address decoder comprises:
applying a first voltage potential to a source region of the MOSFET;
applying a second voltage potential to a drain region of the MOSFET; and
applying a negative gate potential to a gate region of the MOSFET,
wherein applying the first and second voltage potentials and the negative gate potential causes a hot hole injection from the substrate into a gate oxide of the MOSFET.
17. The method of claim 16, wherein applying the first voltage potential to the source region of the MOSFET comprises grounding the source region of the MOSFET.
18. The method of claim 16, wherein applying the second voltage potential to the drain region of the MOSFET comprises grounding the drain region of the MOSFET.
19. The method of claim 16, wherein applying the negative gate potential to the gate region of the MOSFET comprises applying a sufficiently large negative gate potential to form a conduction channel between the source and drain regions of the MOSFET.
20. The method of claim 16, further comprising operating the MOSFET in a forward direction in a programmed state by:
coupling a sourceline to the source region;
coupling a bitline to the drain region; and
applying a gate potential to the gate region such that a conduction channel is formed between the source region and the drain region.
21. The method of claim 14, wherein erasing the MOSFET associated with a redundant row of the address decoder comprises using reverse hot hole injection to remove the trapped positive charge from the gate oxide of the MOSFET associated with the redundant row of the address decoder.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A wavelength dispersion compensation system for compensating wavelength dispersion from which light suffers from being transmitted through an optical fiber, comprising:
a plurality of wavelength dispersion compensation units, each compensating for a wavelength of each order; and
a connection unit sequentially passing the light through the plurality of wavelength dispersion compensation units.
2. The wavelength dispersion compensation system according to claim 1, wherein
at least one of the plurality of wavelength dispersion compensation units can be replaced with at least one returning unit returning the light without wavelength dispersion compensation.
3. The wavelength dispersion compensation system according to claim 1, wherein
a returning unit is provided with a mirror set to return inputted light without modifying an optical axis of the light.
4. The wavelength dispersion compensation system according to claim 1, wherein
said connection unit is provided with an optical circulator.
5. The wavelength dispersion compensation system according to claim 1, wherein
each of said plurality of wavelength dispersion compensation units further comprises a VIPA plate and a reflecting mirror causing transmission delay of light outputted from the VIPA plate by returning the light to the VIPA plate.
6. The wavelength dispersion compensation system according to claim 1, wherein
each of said plurality of wavelength dispersion compensation units comprises a transmission type diffraction grating and a reflecting mirror causing transmission delay of light outputted from a VIPA plate by returning the light to the VIPA plate.
7. The wavelength dispersion compensation system according to claim 5 or 6, wherein
a shape of a reflection surface of the reflecting mirror is determined by solving both a first equation for representing a wavelength dispersion characteristic obtained by expressing a slope of the reflection surface with a differential amount and tracing light outputted from the VIPA plate or transmission type diffraction grating from where the light is reflected on the reflection plane to where the light couples to the VIPA plate or transmission type diffraction grating again and a second equation obtained by assigning a fact that the inverted characteristic of wavelength dispersion characteristic to be compensated is equal to what is expressed by a function having a wavelength as a variable.