1. An optical signal connection apparatus for connecting first and second optical signal transmission lines to first and second routers, respectively, the first and second routers being configured to handle both optical signals and electrical signals, the optical signal connection apparatus comprising a first node and a second node,
wherein the first node includes:
a first port that is coupled to the first router via the first optical signal transmission line, the first port being configured to handle a first type of optical signals associated with the first router, the first optical signal transmission line defining a first communication link,
a first line-setting unit configured to couple the first and second nodes to enable data transfer between the first and second nodes using optical signals,
a first control unit to control the first line-setting unit in setting an optical communication link between the first and second nodes, and
a first signal-type storage unit configured to store first information on the first type of optical signals that the first port is configured to handle;
wherein the second node includes a second port that is coupled to the second router via the second optical signal transmission line, the second port being configured to handle a second type of optical signals associated with the second router, the second optical signal transmission line defining a second communication link, wherein the first information is compared with second information on the second type of optical signal to determine whether the first and second communication links are compatible to each other,
wherein the first and second information are transmitted to a management apparatus that is remotely located from the connection apparatus, the management apparatus using the first and second information to determine whether the first and second communication links are compatible to each other.
2. The optical signal connection apparatus of claim 1, wherein the first control unit retrieves and transmits the first information in response to a request for signal-type information from the management apparatus.
3. The optical signal connection apparatus of claim 1, wherein the first information includes frame configuration information of an optical signal.
4. The optical signal connection apparatus of claim 1, wherein the first information includes frame configuration information, mapping method information, and protocol type information of an optical signal.
5. The optical signal connection apparatus of claim 1, wherein the second node further comprises:
a second signal-type storage unit configured to store the second information on the second type of optical signals that the second port is configured to handle.
6. The optical signal connection apparatus of claim 5, wherein the second node further comprises:
a second line-setting unit configured to couple the first and second nodes to enable data communication between the first and second nodes using optical signals, and
a second control unit to control the second line-setting unit in setting the optical communication link between the first and second nodes.
7. The optical signal connection apparatus according to claim 1, wherein the first information includes the propagation velocity and protocol type of an optical signal.
8. The optical signal connection apparatus according to claim 1, the connection apparatus further comprising:
a signal-type recognition unit configured to use the first and second information to determine whether a communication incompatibility exists between the first and second communication links.
9. The optical signal connection apparatus of claim 8, wherein the signal-type recognition unit is configured to recognize types of optical signals passing through the first port by monitoring optical signal passing through the first port,
wherein information obtained on the signal types by the signal-type recognition unit is provided to the first control unit to enable the first control unit to determine whether there is communication incompatibility,
wherein the management apparatus is notified if the first control unit determines there is communication incompatibility.
10. The optical signal connection apparatus according to claim 9, the connection apparatus further comprising:
a display unit for displaying a message indicating communication incompatibility.
11. The optical signal connection apparatus according to claim 10, wherein the display unit displays information on signal types that are determined to be incompatible.
12. The optical signal connection apparatus according to claim 1, the connection apparatus further comprising input device for inputting the first and second information.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer system comprising:
a central processing unit;
a core logic chipset coupled to the central processing unit;
a peripheral component interconnect (PCI) bus coupled to the core logic chipset and configured to:
operate on a sequential series of clock cycles;
implement registered PCI bus arbitration rules and bus width rules according to a registered PCI protocol;
a registered PCI device connected to the PCI bus and configured to:
operate according to the registered PCI protocol;
issue a first command on a first clock cycle of the PCI bus according to the registered PCI protocol; and
issue a second command on a second clock cycle of the PCI bus according to the registered PCI protocol, wherein the second command is an extended command to the first command and is associated with a split completion issued on a CBE3:0# portion of the PCI bus.
2. The computer system of claim 1, wherein the second command is a Split Completion Exception Message command and the second command being of transaction type Byte-enable and of extended command type validated.
3. The computer system of claim 1, wherein signals on the CBE3:0# portion of the PCI bus have a value of 0011 to indicate that the second command is a split completion exception message command.
4. The computer system of claim 1, comprising:
a host bus coupled between the central processing unit and the core logic chipset; and
a system memory bus coupled between the core logic chipset and a system memory.
5. The computer system of claim 4, wherein the core logic chipset comprises a plurality of interface bridges, wherein at least one of the plurality of interface bridges is configured as an interface bridge between two of the host bus, the system memory bus, or the PCI bus.
6. The computer system of claim 1, wherein signals on the CBE3:0# portion of the PCI bus have a value of 1011 to indicate that the second command is a split completion command.
7. A computer system comprising:
a central processing unit;
a core logic chipset coupled to the central processing unit;
a peripheral component interconnect (PCI) bus coupled to the core logic chipset and configured to implement bus arbitration rules and bus width rules according to a registered PCI protocol;
a registered PCI device connected to the PCI bus and configured to:
operate according to the registered PCI protocol;
issue a first command on a first clock cycle of the PCI bus according to the registered PCI protocol; and
issue a second command on a second clock cycle of the PCI bus according to the registered PCI protocol, wherein the second command is an extended command to the first command and the second command is a command of transaction type byte count.
8. The computer system of claim 7, wherein a plurality of signals on a CBE3:0# portion of the PCI bus have a value of one of 1000, 1001 or 1010 to indicate that the second command is a reserved command of transaction type byte count and of extended command type validated.
9. The computer system of claim 7, wherein a plurality of signals on a CBE3:0# portion of the PCI bus have a value of one of 1000, 1001, 1010, 1011, 1100, 1101, 1110 or 1111 to indicate that the second command is a command of transaction type byte count.
10. The computer system of claim 7, wherein a plurality of signals on a CBE3:0# portion of the PCI bus have a value of one of 1100, 1101, 1110 or 1111 to indicate that the second command is a command of transaction type byte count and of extended command type immediate.
11. The computer system of claim 7, wherein the PCI bus is further configured to issue an attribute during the second clock cycle on an addressdata (AD) portion of the PCI bus associated with byte count.
12. The computer system of claim 11, wherein the AD portion of the PCI bus is adapted to issue a plurality of signals with one of the plurality of signals being a byte count attribute phase signal.
13. The computer system of claim 12, wherein the plurality of signals comprise 64 signals and wherein a lower ten bits of the byte count attribute phase signal is issued on AD26:17.
14. A computer system comprising:
a central processing unit;
a core logic chipset coupled to the central processing unit;
a peripheral component interconnect (PCI) bus coupled to the core logic chipset and configured to implement bus arbitration rules and bus width rules;
a PCI device connected to the PCI bus and configured to:
operate according to a registered PCI protocol;
issue a first command on a first clock cycle of the PCI bus;
issue a second command on a second clock cycle of the PCI bus,
wherein the second command is an extended command to the first command; and
issue an attribute during the second clock cycle on an addressdata (AD) portion of the PCI bus associated with relaxed ordering.
15. The computer system of claim 14, wherein the AD portion of the PCI bus is adapted to issue 64 signals, wherein a relaxed ordering attribute phase signal is issued on AD2.
16. The computer system of claim 14, further comprising:
a host bus coupled between the central processing unit and the core logic chipset; and
a system memory bus couples the core logic chipset to a system memory.
17. A computer system comprising:
a central processing unit;
a core logic chipset coupled to the central processing unit;
a peripheral component interconnect (PCI) bus coupled to the core logic chipset and configured to implement bus arbitration rules and bus width rules based on a registered PCI protocol;
a PCI device connected to the PCI bus and configured to:
issue a first command on a first clock cycle of the PCI bus based on the registered PCI protocol;
issue a second command on a second clock cycle of the PCI bus based on the registered PCI protocol, wherein the second command is an extended command to the first command; and
issue an attribute during the second clock cycle on an addressdata (AD) portion of the PCI bus associated with a bus number.
18. The computer system of claim 17, wherein the AD portion of the PCI bus is adapted to issue a plurality of signals with one of the plurality of signals being an initiator bus number attribute phase signal.
19. The computer system of claim 18, wherein the plurality of signals comprise 64 signals and wherein a lower five bits of the initiator bus number attribute phase signal are issued on AD8:4.
20. The computer system of claim 18, wherein the plurality of signals comprise 64 signals and wherein an upper three bits of the initiator bus number attribute phase signal are issued on AD34:32.
21. A computer system comprising:
a central processing unit;
a core logic chipset coupled to the central processing unit;
a peripheral component interconnect (PCI) bus coupled to the core logic chipset and configured to implement bus arbitration rules and bus width rules;
a registered PCI device connected to the PCI bus and configured to:
operate according to a registered PCI protocol; and
issue a first command on a first clock cycle of the PCI bus according to the registered PCI protocol;
issue a second command on a second clock cycle of the PCI bus according to the registered PCI protocol, wherein the second command is an extended command to the first command; and
issue an attribute during the second clock cycle on an addressdata (AD) portion of the PCI bus associated with an initiator number.
22. The computer system of claim 21, wherein the AD portion of the PCI bus is adapted to issue a plurality of signals with one of the plurality of signals being an initiator number attribute phase signal.
23. The computer system of claim 22, wherein the plurality of signals comprise 64 signals and wherein a lower five bits of the initiator number attribute phase signal are issued on AD13:9.
24. The computer system of claim 22, wherein the plurality of signals comprise 64 signals and wherein an upper one bit of the initiator number attribute phase signal is issued on AD35.
25. A computer system comprising:
a central processing unit;
a core logic chipset coupled to the central processing unit;
a peripheral component interconnect (PCI) bus coupled to the core logic chipset and configured to:
operate on a sequential series of clock cycles; and
implement registered PCI bus arbitration rules and bus width rules according to a registered PCI protocol;
a registered PCI device connected to the PCI bus and configured to:
operate according to the registered PCI protocol;
issue a first command on a first clock cycle of the PCI bus according to the registered PCI protocol;
issue a second command on a second clock cycle of the PCI bus according to the registered PCI protocol, wherein the second command is an extended command to the first command; and
issue an attribute during the second clock cycle on an addressdata (AD) portion of the PCI bus associated with a sequence number.
26. The computer system of claim 25, wherein the AD portion of the PCI bus is adapted to issue a plurality of signals with one of the plurality of signals being a sequence number attribute phase signal.
27. The computer system of claim 26, wherein the plurality of signals comprise 64 signals and wherein a lower three bits of a sequence number attribute phase signal are issued on AD16:14.
28. The computer system of claim 26, wherein the plurality of signals comprise 64 signals and wherein an upper one bit of the sequence number attribute phase signal is issued on AD36.