1. A method comprising:
forming a first trench in a substrate, the first trench having a first width;
forming a first oxide layer on side surfaces of the first trench;
forming a second trench in the substrate, below the first trench, the second trench having a second width less than the first width;
forming a second oxide layer on side and bottom surfaces of the second trench;
forming spacers on sides of the first and second trenches;
removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers;
filling the first and second trenches with a first poly-silicon to form a drain region;
removing the spacers, exposing side surfaces of the first poly-silicon;
forming a third oxide layer on the side surfaces and a top surface of the first poly-silicon; and
filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.
2. The method according to claim 1, comprising:
doping the substrate around the second trench, after forming the second trench, to form a drift region.
3. The method according to claim 1, comprising:
doping the substrate beneath the bottom surface of the second trench, after forming the spacers, to form a N+ region.
4. The method according to claim 1, comprising:
forming nitride spacers on the sides of the first trench after forming the first oxide layer; and
forming the second trench using the nitride spacers as a hard mask.
5. The method according to claim 1, comprising:
forming a poly-silicon layer on the sides and bottom of the first and second trenches before forming the spacers.
6. The method according to claim 5, comprising:
forming the third oxide layer and a fourth oxide layer on side surfaces of the first and second trenches by respectively oxidizing the first poly-silicon and the poly-silicon layer; and
removing the fourth oxide layer and the nitride spacers before filling the remainder with the second poly-silicon.
7. The method according to claim 6, comprising:
forming a fifth oxide layer on the substrate after filling the remainder with the second poly-silicon; and
forming a low voltage transistor andor a medium voltage transistor on the fifth oxide layer.
8. The method according to claim 1, comprising:
forming the second oxide layer to be 500 \u212b to 20,000 \u212b in thickness; and
forming the third oxide layer to be 500 \u212b to 20,000 \u212b in thickness.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A integrated circuit device comprising:
a processor; and
Integrated InputOutput (IIO) logic coupled to the processor,
wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence, wherein the processor and the IIO logic are to each comprise sideband control logic to provide sideband communication support in lieu of removal of a physical link layer circuitry.
2. The device of claim 1, further comprising a power management unit, coupled to the IIO logic to cause the portion of the IIO logic to enter lower power consumption state.
3. The device of claim 1, wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes.
4. The device of claim 3, wherein the plurality of power sequence gating modes are to comprise: static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.
5. The device of claim 4, wherein the static clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic based on: one or more features being disabled during operation or one or more interfaces not being supported.
6. The device of claim 4, wherein the dynamic clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic when the one or more blocks become inactive during runtime.
7. The device of claim 4, wherein the full clock gating mode is to comprise full coarse clock gating one or more blocks of the IIO logic.
8. The device of claim 4, wherein the pre-sleep mode is to comprise preparing a phase locked loop of the IIO logic for shut down.
9. The device of claim 4, wherein the light sleep mode is to comprise shutting down a phase locked loop of the IIO logic.
10. The device of claim 4, wherein the deep sleep mode is to comprise power gating one or more blocks of the IIO logic.
11. The device of claim 3, wherein the coarse clock gating corresponds to gating off an entire cluster or block of IIO hardware when idle or not in use.
12. The device of claim 1, wherein one or more inactive blocks of the IIO are to be coarse clock gated.
13. The device of claim 12, wherein the one or more inactive blocks are to be determined based on: one or more features being disabled during operation, one or more interfaces not being supported, or one or more blocks are idle as no traffic or transaction is occurring during runtime.
14. The device of claim 1, wherein the processor is to comprise one or more processor cores.
15. A method comprising:
generating a signal from a power management unit of IIO logic to cause at least a portion of an IIO logic to enter a lower power consumption state based on a power reduction sequence,
wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes and wherein the IIO logic comprises sideband control logic to provide sideband communication support in lieu of removal of a physical link layer circuitry.
16. The method of claim 15, wherein the plurality of power sequence gating modes are to comprise: static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.
17. The method of claim 15, further comprising clock gating one or more inactive blocks of the IIO logic based on: one or more features being disabled during operation or one or more interfaces not being supported.
18. The method of claim 15, further comprising clock gating one or more inactive blocks of the IIO logic when the one or more blocks become inactive during runtime.
19. The method of claim 15, further comprising full coarse clock gating one or more blocks of the IIO logic.
20. The method of claim 15, further comprising preparing a phase locked loop of the IIO logic for shut down.
21. The method of claim 15, further comprising shutting down a phase locked loop of the IIO logic.
22. The method of claim 15, further comprising power gating one or more blocks of the IIO logic.
23. The method of claim 15, wherein the coarse clock gating corresponds to gating off an entire cluster or block of IIO hardware when idle or not in use.
24. The method of claim 15, further comprising communicating data between a system memory and one or more IO devices via the IIO logic.
25. A system comprising:
a system memory to store data;
a processor to access the stored data; and
Integrated InputOutput (IIO) logic coupled to the processor,
wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence, wherein the processor and the IIO logic are to each comprise sideband control logic to provide sideband communication support in lieu of removal of a physical link layer circuitry.
26. The system of claim 25, further comprising a power management unit, coupled to the IIO logic to cause the portion of the IIO logic to enter lower power consumption state.
27. The system of claim 25, wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes.
28. The system of claim 27, wherein the plurality of power sequence gating modes are to comprise: static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.
29. The system of claim 28, wherein the static clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic based on: one or more features being disabled during operation or one or more interfaces not being supported.
30. The system of claim 28, wherein the light sleep mode is to comprise shutting down a phase locked loop of the IIO logic.