1. A system for removing accumulations of ice and snow from the bottom of inlet muff of an auxiliary power unit (APU), comprising:
a gull wing fairing mounted within the inlet muff to direct inlet air into an inlet of the APU that has a plurality of perforations to allow air and liquid flow through the fairing into a stagnant air region of the inlet muff below the fairing;
a tracer line comprising tubing that is arranged along a surface of the fairing in a general \u201czigzag\u201d pattern that has an inlet coupled to a primary stream of high pressure hot air and an outlet to warm the fairing sufficiently to melt ice and snow that accumulates in the region of the fairing; and
an ejector with a primary nozzle inlet coupled to the outlet of the tracer line for coupling the primary stream of high pressure hot air into an ejector nozzle and a secondary stream inlet that couples the stagnant air region of the inlet muff below the fairing to an ejector mixing tube to suck a secondary stream of air with ice and snow melt from the bottom of the inlet muff and discharge it from an outlet of the ejector mixing tube.
2. The system of claim 1, wherein the tracer line is mounted along a bottom surface of the fairing.
3. The system of claim 1, wherein the tracer line is mounted along a top surface of the fairing.
4. The system of claim 1, wherein the compressor delivery air is provided by an APU load compressor.
5. The system of claim 1, wherein the compressor delivery air is provided by bleed air from a cycle compressor in an APU power head.
6. The system of claim 1, wherein the primary nozzle inlet and the primary nozzle are positioned within the inlet muff.
7. The system of claim 1, further comprising insulation that covers surfaces of the ejector external to the inlet muff.
8. The system of claim 1, wherein the compressor delivery air supplied to the inlet of the tracer line is regulated with valving to suit environmental conditions.
9. The system of claim 1, wherein the compressor delivery air supplied to the inlet of the tracer line is regulated with an orifice to suit environmental conditions.
10. The system of claim 1, wherein the compressor delivery air supplied to the inlet of the tracer line is regulated with a flow restrictor to suit environmental conditions.
11. The system of claim 1, further comprising a manifold with an inlet coupled to the outlet of the ejector mixing tube, a lower outlet for discharging ice and snow melt from the bottom of the inlet muff, and an upper outlet coupled to the stagnant region of the inlet muff for discharging at least a portion of the primary and secondary air streams back into the muff to assist the tracer line to melt any accumulation of ice and snow within the muff that accumulates in the region of the fairing.
12. The system of claim 11, further comprising insulation that covers the manifold.
13. The system of claim 11, wherein the discharge from the upper outlet to the stagnant region of the inlet muff is regulated with valving to suit environmental conditions.
14. The system of claim 11, wherein the discharge from the upper outlet to the stagnant region of the inlet muff is regulated with an orifice to suit environmental conditions.
15. The system of claim 11, wherein the discharge from the upper outlet to the stagnant region of the inlet muff is regulated with a flow restrictor to suit environmental conditions.
16. A system for removing accumulations of ice and snow from the bottom of inlet muff of an auxiliary power unit (APU), comprising:
a gull wing fairing mounted within the inlet muff to direct inlet air into an inlet of the APU that has a plurality of perforations to allow air and liquid flow through the fairing into a stagnant air region of the inlet muff below the fairing;
a tracer line comprising tubing that is arranged along a bottom surface of the fairing in a general \u201czigzag\u201d pattern that has an inlet coupled to a primary stream of high pressure hot air from an APU load compressor and an outlet to warm the fairing sufficiently to melt ice and snow that accumulates in the region of the fairing; and
an ejector with a primary nozzle inlet coupled to the outlet of the tracer line for coupling the primary stream of high pressure hot air into an ejector nozzle, the primary nozzle inlet and the primary nozzle both positioned within the inlet muff, and a secondary stream inlet that couples the stagnant air region of the inlet muff below the fairing to an ejector mixing tube to suck a secondary stream of air with ice and snow melt from the bottom of the inlet muff and discharge it from an outlet of the ejector mixing tube.
17. The system of claim 16, further comprising insulation covering surfaces of the ejector external to the inlet muff.
18. The system of claim 16, wherein the compressor delivery air supplied to the inlet of the tracer line is regulated with valving to suit environmental conditions.
19. The system of claim 16, wherein the compressor delivery air supplied to the inlet of the tracer line is regulated with an orifice to suit environmental conditions.
20. The system of claim 16, wherein the compressor delivery air supplied to the inlet of the tracer line is regulated with a flow restrictor to suit environmental conditions.
21. The system of claim 16, further comprising a manifold with an inlet coupled to the outlet of the ejector mixing tube, a lower outlet for discharging ice and snow melt from the bottom of the inlet muff, and an upper outlet coupled to the stagnant region of the inlet muff for discharging at least a portion of the primary and secondary air streams back into the muff to assist the tracer line to melt any accumulation of ice and snow within the muff that accumulates in the region of the fairing.
22. The system of claim 21, further comprising insulation that covers the manifold.
23. The system of claim 21, wherein the discharge from the upper outlet to the stagnant region of the inlet muff is regulated with valving to suit environmental conditions.
24. The system of claim 21, wherein the discharge from the upper outlet to the stagnant region of the inlet muff is regulated with an orifice to suit environmental conditions.
25. The system of claim 21, wherein the discharge from the upper outlet to the stagnant region of the inlet muff is regulated with a flow restrictor to suit environmental conditions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory cell comprising:
a thyristor device including doped regions of opposite polarity;
a first word line providing read and write access to the memory cell; and
a second word line located adjacent to and separated by an insulative material from at least one of the doped regions of the thyristor device and used for write operation to the memory cell by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and from the low conductance state to the high conductance state.
2. The memory cell of claim 1, further comprising a transistor, wherein the read and write access is provided by the transistor with its gate forming at least part of the first word line.
3. The memory cell of claim 2, wherein the transistor is a MOSFET transistor.
4. The memory cell of claim 1, wherein the second word line enhances the switching of the thyristor device by substantially improving the switching speed of the thyristor device from the high conductance state to the low conductance state.
5. The memory cell of claim 1, wherein the second word line is adapted to enhance the switching of the thyristor device by substantially reducing the voltage requirement of the thyristor device for switching from the low conductance state to the high conductance state.
6. The memory cell of claim 1, wherein at least part of the cell is arranged in a vertical configuration extending above a substrate surface.
7. The memory cell of claim 1, wherein at least part of the cell is arranged in a vertical configuration extending below a substrate surface.
8. The memory cell of claim 1, wherein at least part of the cell is arranged in a planar configuration parallel to a substrate surface.
9. The memory cell of claim 8, wherein the substrate surface is part of a silicon-on-insulator substrate.
10. The memory cell of claim 2, wherein the transistor and the thyristor device are arranged in a planar configuration parallel to a substrate surface.
11. The memory cell of claim 10, wherein the substrate surface is part of a silicon-on-insulator substrate.
12. A memory array comprising:
a first and a second word line; and
a plurality of memory cells, each memory cell comprising a thyristor device including doped regions of opposite polarity, wherein
the first word line providing read and write access to the memory cell; and
a portion of the second word line located adjacent to and separated by an insulative material from at least one of the doped regions of the thyristor device and used for write operation to the memory cell by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and from the low conductance state to the high conductance state.
13. The memory array of claim 12, wherein the memory cell further comprises a transistor, and wherein the read and write access is provided by the transistor with its gate forming at least part of the first word line.
14. The memory array of claim 13, wherein the transistor is a MOSFET transistor.
15. The memory array of claim 12, wherein the second word line enhances the switching of the thyristor device by substantially improving the switching speed of the thyristor device from the high conductance state to the low conductance state.
16. The memory array of claim 12, wherein the second word line enhances the switching of the thyristor device by substantially reducing the voltage requirement of the thyristor device for switching from the low conductance state to the high conductance state.
17. The memory array of claim 12, wherein at least part of the memory cell is arranged in a vertical configuration extending above a substrate surface.
18. The memory array of claim 12, wherein at least part of the memory cell is arranged in a vertical configuration extending below a substrate surface.
19. The memory array of claim 12, wherein at least part of the memory cell is arranged in a planar configuration parallel to a substrate surface.
20. The memory array of claim 19, wherein the substrate surface is part of a silicon-on-insulator substrate.
21. The memory array of claim 13, wherein the transistor and the thyristor device are arranged in a planar configuration parallel to a substrate surface.
22. The memory array of claim 21, wherein the substrate surface is part of a silicon-on-insulator substrate.