1. A MTJ nanopillar structure formed on a bottom electrode in a STT-RAM device, comprising:
(a) a synthetic anti-ferromagnetic (SyAF) pinned layer with an AP2couplingAP1 configuration wherein AP2 and AP1 are ferromagnetic layers separated by a coupling layer;
(b) a MgO tunnel barrier that forms an interface with the AP1 layer; and
(c) a composite free layer that forms an interface with the MgO tunnel barrier, and having a FL1NCCFL2, FL1NCCFL2NCC, or FL1NCCFL2NCCFL3 configuration wherein FL1, FL2, and FL3 are magnetic layers and NCC is a nanocurrent channel layer comprised of R(M) grains having a certain grain diameter size that are formed in a metal (M) oxide, nitride, or oxynitride insulator matrix, R is Fe, Ni, or Co, or a combination thereof, and M is a metal.
2. The MTJ nanopillar structure of claim 1 wherein FL1, FL2, and FL3 layers are comprised of CoFeB, and interfaces between said CoFeB layers and the one or more NCC layers enhance interfacial perpendicular anisotropy compared with that of a single CoFeB free layer having no NCC component.
3. The MTJ nanopillar structure of claim 1 wherein the composite free layer has a FL1NCCFL2 configuration wherein said FL1 layer has a thickness from about 14.5 to 15.5 Angstroms and contacts the MgO tunnel barrier and is comprised of CoSFe(80-S)B20 where s is from about 10 to 20, the FL2 layer is made of CoSFe(80-S)B20 with a thickness between about 6 and 8.5 Angstroms, and the NCC layer is comprised of Fe(20%)-SiO2 with a thickness from about 6 to 10 Angstroms.
4. The MTJ nanopillar structure of claim 1 wherein the composite free layer has a FL1NCC1FL2NCC2FL3 configuration wherein said FL1 layer has a thickness from about 13.5 to 14.5 Angstroms and contacts the MgO tunnel barrier and is comprised of CoSFe(80-S)B20 where s is from about 10 to 20, the FL2 and FL3 layers are comprised of CoSFe(80-S))B20 wherein the FL2 layer is from about 4.5 to 5.5 Angstroms thick and the FL3 layer is from about 6 to 8.5 Angstroms thick, and the NCC layers are comprised of Fe(20%)-SiO2 with a thickness from about 6 to 10 Angstroms.
5. The MTJ nanopillar structure of claim 1 wherein the composite free layer has a FL1NCC1FL2NCC2 configuration wherein said FL1 layer has a thickness from about 14.5 to 15.5 Angstroms and contacts the MgO tunnel barrier and is comprised of CoSFe(80-S))B20 where s is from about 10 to 20, the FL2 layer is comprised of CoSFe(80-S)B20 and has a thickness between about 6 to 8.5 Angstroms, and the NCC layers are comprised of Fe(20%)-SiO2 with a thickness from about 6 to 10 Angstroms.
6. The MTJ nanopillar structure of claim 1 wherein the MTJ nanopillar structure is comprised of a seed layer, an anti-ferromagnetic (AFM) layer, the SyAF pinned layer, the MgO tunnel barrier, the composite free layer, a capping layer, and a hard mask layer that are sequentially formed on the bottom electrode.
7. The MTJ nanopillar structure of claim 1 wherein the SyAF pinned layer has a CoFeBRuCoFeBCoFe configuration wherein the AP1 layer is comprised of CoFeBCoFe and the CoFe layer contacts the MgO tunnel barrier.
8. The MTJ nanopillar structure of claim 6 wherein the capping layer is made of Ru and the hard mask layer is has a MnPtTa configuration wherein the Ta layer is an uppermost layer in the MTJ nanopillar structure.
9. The MTJ nanopillar structure of claim 1 wherein all of the FL1, FL2, and FL3 layers are comprised of Co10Fe70B20, and each NCC layer has a Fe(20%)-SiO2 composition.
10. The MTJ nanopillar structure of claim 1 wherein R is Fe, M is Si, and the certain diameter grain size is about 10 Angstroms.
11. A MTJ nanopillar structure formed on a bottom electrode in a STT-RAM device, comprising:
(a) a synthetic anti-ferromagnetic (SyAF) pinned layer with an AP2couplingAP1 configuration;
(b) a MgO tunnel barrier that forms an interface with the AP1 layer; and
(c) a composite free layer that forms an interface with the MgO tunnel barrier, and having a FL1NCCFL1, FL1NCCFL2NCC, or FL1NCCFL2NCCFL3 configuration wherein FL1, FL2, and FL3 are all magnetic layers comprised of Co10Fe70B20 and NCC is a nanocurrent channel layer comprised of R(M) grains that are formed in a metal (M) oxide, nitride, or oxynitride insulator matrix, and R is Fe, Ni, or Co, or a combination thereof.
12. The MTJ nanopillar structure of claim 11 wherein each NCC nanocurrent channel layer has a thickness between about 6 and 10 Angstroms and is comprised of Fe(20%)-SiO2.
13. A method of forming a STT-RAM MTJ nanopillar on a substrate comprised of a bottom electrode, comprising:
(a) sequentially forming a MTJ stack of layers comprised of a seed layer, an anti-ferromagnetic (AFM) layer, a SyAF pinned layer, a MgO tunnel barrier, a composite free layer, and a capping layer on said bottom electrode, said composite free layer has a FL1NCCFL2, FL1NCCFL2NCC, or FL1NCCFL2NCCFL3 configuration wherein FL1, FL2, and FL3 are magnetic layers and NCC is a nanocurrent channel layer comprised of R(M) grains with a certain grain diameter size that are formed in a metal (M) oxide, nitride, or oxynitride insulator matrix, R is Fe, Ni, or Co, or a combination thereof, and M is a metal;
(b) annealing said MTJ stack of layers; and
(c) patterning said MTJ stack of layers.
14. The method of claim 13 wherein the SyAF pinned layer has an AP2couplingAP1 configuration wherein the AP2 layer contacts the AFM layer, the coupling layer is Ru, and the AP1 layer is CoFeB, CoFe, or a combination thereof.
15. The method of claim 13 wherein the MgO tunnel barrier is fabricated by a process comprising:
(a) sputter depositing a first Mg layer on the AP1 layer;
(b) oxidizing the first Mg layer with a natural oxidation (NOX) process;
(c) sputter depositing a second Mg layer on the oxidized first Mg layer;
(d) forming an oxygen surfactant layer on the second Mg layer; and
(e) sputter depositing a third Mg layer on the oxygen surfactant layer.
16. The method of claim 13 wherein the composite free layer has a FL1NCCFL2 configuration, said FL1 layer has a thickness from about 14.5 to 15.5 Angstroms and contacts the MgO tunnel barrier and is comprised of CoSFe(80-S)B20 where s is from about 10 to 20, the FL2 layer is made of CoSFe(80-S)B20 with a thickness between about 6 and 8.5 Angstroms, and the NCC layer is comprised of Fe(20%)-SiO2 with a thickness from about 6 to 10 Angstroms.
17. The method of claim 13 wherein the composite free layer has a FL1NCC1FL2NCC2FL3 configuration, said FL1 layer has a thickness from about 13.5 to 14.5 Angstroms and contacts the MgO tunnel barrier and is comprised of CoSFe(80-S)B20 where s is from about 10 to 20, the FL2 and FL3 layers are comprised of CoSFe(80-S)B20 wherein the FL2 layer is from about 4.5 to 5.5 Angstroms thick and the FL3 layer is from about 6 to 8.5 Angstroms thick, and the NCC layers are comprised of Fe(20%)-SiO2 with a thickness from about 6 to 10 Angstroms.
18. The method of claim 13 wherein the composite free layer has a FL1NCC1FL2NCC2 configuration, said FL1 layer has a thickness from about 14.5 to 15.5 Angstroms and contacts the MgO tunnel barrier and is comprised of CoSFe(80-S)B20 where s is from about 10 to 20, the FL2 layer is comprised of CoSFe(80-S)B20 and has a thickness between about 6 to 8.5 Angstroms, and the NCC layers are comprised of Fe(20%)-SiO2 with a thickness from about 6 to 10 Angstroms.
19. The method of claim 13 wherein the insulator matrix is SiO2, R is Fe, and the Fe(Si) certain grain minimum diameter size is about 10 Angstroms.
20. The method of claim 13 wherein each of the FL1, FL2, and FL3 layers is comprised of Co10Fe70B20.
21. The method of claim 13 wherein the FL1, FL2, and FL3 layers are sputter deposited with a process comprising a power of about 15 Watts and an Ar flow rate of about 40 standard cubic centimeters per minute (sccm).
22. The method of claim 13 wherein annealing said MTJ stack of layers comprises a temperature from about 300\xb0 C. to 360\xb0 C., and a magnetic field of about 5000 to 10000 Oe for a period of about 1 to 5 hours.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A focal plane array (FPA), comprising:
a package body extending continuously between an upper surface and a lower surface to define outer sides, the package body having a cavity formed therein to define inner sidewalls and an inner surface extending between the inner sidewalls;
a dielectric attachment material having a first surface disposed directly against the inner surface of the package body and a second surface disposed directly against a read out integrated circuit (ROIC) comprising a circuit side having circuitry thereon;
a photodiode array (PDA) comprising circuitry including a plurality of photodiodes; and
a conductor interposed between the PDA and the ROIC, wherein the conductor electrically couples circuitry on the PDA to circuitry on the ROIC;
an optically transparent lid including an inner surface extending continuously between a pair of opposing outer edges, the outer edges attached to the outer sides of package body via a hermetic sealing material interposed between the optically transparent lid and the outer sides, wherein the package body and the lid define an interior of the FPA, and wherein the PDA and the ROIC are sealed within the interior of the FPA such that the inner surface of the optically transparent lid extends beyond the PDA and the ROIC; and
a plurality of conductive traces on an interior surface of the lid, wherein the circuitry on the ROIC is electrically coupled to the plurality of conductive traces on the interior surface of the lid, the plurality of conductive traces including a first trace and an opposing second trace, wherein the dielectric layer is interposed between the first and second traces so as to physically attach the optically transparent lid to the PDA.
2. The focal plane array of claim 1, further comprising a plurality of trenches on the interior surface of the lid, wherein the plurality of traces are within the plurality of trenches.
3. The focal plane array of claim 1, wherein the package body is a chip carrier.
4. The focal plane array of claim 1, wherein the package body is a printed circuit board.
5. The focal plane array of claim 1, wherein:
the PDA comprises no bond wires that electrically couple the PDA to the ROIC; and
the PDA comprises no bond wires that electrically couple the ROIC to the package body.
6. The focal plane array of claim 2, further comprising a plurality of traces within the package body, wherein the plurality of traces on the interior surface of the lid are electrically coupled with the plurality of traces within the package body.
7. The focal plane array of claim 6, further comprising a dielectric that physically attaches the PDA to the interior surface of the lid.
8. The focal plane array of claim 7, wherein the plurality of bumps are within an outside perimeter of the PDA.
9. The focal plane array of claim 8, wherein:
the PDA comprises no bond wires that electrically couple the PDA to the ROIC; and
the PDA comprises no bond wires that electrically couple the ROIC to the package body.
10. A method for forming a focal plane array (FPA), comprising:
physically contacting a first plurality of landing pads on a photodiode array (PDA) to a conductor;
physically contacting a second plurality of landing pads on a read out integrated circuit (ROIC) to the conductor, wherein the conductor is interposed between the PDA and the ROIC;
curing the conductor to physically attach the PDA and the ROIC to each other and to electrically couple circuitry on the PDA with circuitry on the ROIC; and
attaching the PDA to an optically transparent lid such that outer edges of the optically transparent lid extend beyond sides of the PDA;
attaching the optically transparent lid to an upper surface of a package body that extends between opposing sidewalls, the outer edges of the optically transparent lid sealed to the upper surface via a hermetic sealing material interposed between the outer edges of the optically transparent lid and the sidewalls;
electrically coupling a first end of a first plurality of conductive traces on the lid to the circuitry on the ROIC, the first plurality of conductive traces including a first upper trace interposed between a first sidewall of the opposing sidewalls and a first side of the PDA, and a second upper trace interposed between a second sidewall of the opposing sidewalls and a second side of the PDA opposite the first side;
electrically coupling a second end of the first plurality of conductive traces on the lid to a second plurality of conductive traces within the package body, the second plurality of conductive traces including a first lower trace interposed between the first sidewall of the opposing sidewalls and a first side edge of the ROIC, and a second lower trace interposed between a second sidewall of the opposing sidewalls and a second side edge of the ROIC opposite the first side; and
prior to attaching the optically transparent lid, depositing a dielectric attachment material having a first surface disposed directly against the inner surface of the package body and a second surface disposed directly against a read out ROIC comprising a circuit side having circuitry thereon, wherein the dielectric layer is interposed between the first and second traces so as to physically attach the optically transparent lid to the PDA.
11. The method of claim 10, further comprising electrically coupling the circuitry on the ROIC to a plurality of castellations on an exterior surface of the package body during the electrical coupling of the first end of the first plurality of conductive traces on the lid to the circuitry on the ROIC and the electrical coupling of the second end of the first plurality of conductive traces on the lid to the second plurality of conductive traces within the package body.
12. The method of claim 10, further comprising:
providing a chip carrier package body; and
attaching the optically transparent lid to the chip carrier package body.
13. The method of claim 10, further comprising:
providing a printed circuit board package body; and
attaching the optically transparent lid to the printed circuit board package body.
14. The method of claim 10, further comprising:
forming the FPA attached to a plurality of other FPAs as part of a wafer scale integration process; and
singularizing the plurality of FPAs to form a plurality of discrete FPAs.
15. The method of claim 11, further comprising:
forming a plurality of trenches on the interior surface of the lid;
forming a blanket metal layer over the interior surface of the lid and within the plurality of trenches on the interior surface of the lid; and
planarizing the blanket metal layer to form the plurality of conductive traces.