1. A driving method of a liquid crystal display (LCD) monitor, the LCD monitor comprising:
an LCD panel for displaying a plurality of pixels arranged in a matrix format;
a positive buffer circuit for driving the pixels with a positive voltage;
a negative buffer circuit for driving the pixels with a negative voltage;
a detector for receiving a horizontal synchronization signal and a polarity signal, and for comparing states of the polarity signal at two successive triggers of the horizontal synchronization signal; and
a controller connected to the detector, the positive buffer circuit, and the negative buffer circuit for controlling operation of the positive buffer circuit and the negative buffer circuit according to an output of the detector;
the driving method comprising:
using the controller to control either the positive buffer circuit or the negative buffer circuit for driving two adjacent pixels, which are located in the same column but different rows on the LCD panel corresponding to the two successive triggers of the horizontal synchronization signal, with voltages of the same polarity when the detector detects that states of the polarity signal at two successive triggers of the horizontal synchronization signal are the same so that the positive buffer circuit continuously drives the pixels with the positive voltage and the negative buffer circuit continuously drives the pixels with the negative voltage; and
using the controller to control the positive buffer circuit and the negative buffer circuit for driving two adjacent pixels, which are located in the same column but different rows on the LCD panel corresponding to two successive triggers of the horizontal synchronization signal, with voltages of opposite polarities when the detector detects that two states of the polarity signal at two successive triggers of the horizontal synchronization signal differ.
2. The driving method of claim 1 wherein the pixel to be driven with a positive voltage is precharged to a predetermined positive level before being driven, and the pixel to be driven with a negative voltage is precharged to a predetermined negative level before being driven.
3. The driving method of claim 2 wherein the positive buffer circuit comprises a first precharge circuit for providing the predetermined positive level, and the negative buffer circuit comprises a second precharge circuit for providing the predetermined negative level.
4. The driving method of claim 3 wherein the first precharge circuit and the second precharge circuit are source followers.
5. The driving method of claim 1 wherein the detector comprises two latch circuits for holding the corresponding states of the polarity signal at two successive triggers of the horizontal synchronization signal, and a logic circuit for comparing two states of the polarity signal at two successive triggers of the horizontal synchronization signal.
6. The driving method of claim 1 wherein each of the positive buffer circuit and the negative buffer comprises a class-A operational amplifier buffer for driving pixels.
7. A liquid crystal display (LCD) monitor comprising: an LCD panel for displaying a plurality of pixels arranged in a matrix format;
a positive buffer circuit for driving the pixels with a positive voltage;
a negative buffer circuit for driving the pixels with a negative voltage;
a detector for receiving a horizontal synchronization signal and a polarity signal, and for comparing states of the polarity signal at two successive triggers of the horizontal synchronization signal; and
a controller connected to the detector, the positive buffer circuit, and the negative buffer circuit for controlling operation of the positive buffer circuit and the negative buffer circuit according to an output of the detector;
wherein the controller controls either the positive buffer circuit or the negative buffer circuit for driving two adjacent pixels, which are located in the same column but different rows on the LCD panel corresponding to the two successive triggers of the horizontal synchronization signal, with voltages of the same polarity when the detector detects that states of the polarity signal at two successive triggers of the horizontal synchronization signal are the same so that the positive buffer circuit continuously drives the pixels with the positive voltage and the negative buffer circuit continuously drives the pixels with the negative voltage, and the controller controls the positive buffer circuit and the negative buffer circuit for driving two adjacent pixels, which are located in the same column but different rows on the LCD panel corresponding to two successive triggers of the horizontal synchronization signal, with voltages of opposite polarities when the detector detects that two states of the polarity signal at two successive triggers of the horizontal synchronization signal differ.
8. The liquid crystal display monitor of claim 7 wherein the pixel to be driven with a positive voltage is precharged to a predetermined positive level before being driven, and the pixel to be driven with a negative voltage is precharged to a predetermined negative level before being driven.
9. The liquid crystal display monitor of claim 8 wherein the positive buffer circuit comprises a first precharge circuit for providing the predetermined positive level, and the negative buffer circuit comprises a second precharge circuit for providing the predetermined negative level.
10. The liquid crystal display monitor of claim 9 wherein the first precharge circuit and the second precharge circuit are source followers.
11. The liquid crystal display monitor of claim 7 wherein the detector comprises two latch circuits for holding the corresponding states of the polarity signal at two successive triggers of the horizontal synchronization signal, and a logic circuit for comparing two states of the polarity signal at two successive triggers of the horizontal synchronization signal.
12. The liquid crystal display monitor of claim 7 wherein each of the positive buffer circuit and the negative buffer circuit comprises a class-A operational amplifier buffer for driving the pixels.
13. A driving circuit of a liquid crystal display (LCD) monitor, the LCD monitor comprising an LCD panel for displaying a plurality of pixels arranged in a matrix format, the driving circuit comprising:
a positive buffer circuit for driving the pixels with a positive voltage;
a negative buffer circuit for driving the pixels with a negative voltage;
a detector for receiving a horizontal synchronization signal and a polarity signal, the detector comprising:
two latch circuits for holding the corresponding states of the polarity signal at two successive triggers of the horizontal synchronization signal; and
a logic circuit for comparing two states of the polarity signal at two successive triggers of the horizontal synchronization signal; and
a controller connected to the detector, the positive buffer circuit, and the negative output buffer for controlling operation of the positive buffer circuit and the negative buffer circuit according to an output of the detector;
wherein the controller controls either the positive buffer circuit or the negative buffer circuit for driving two adjacent pixels, which are located in the same column but different rows on the LCD panel corresponding to the two successive triggers of the horizontal synchronization signal, with voltages of the same polarity when the detector detects that states of the polarity signal at two successive triggers of the horizontal synchronization signal are the same so that the positive buffer circuit continuously drives the pixels with the positive voltage and the negative buffer circuit continuously drives the pixels with the negative voltage, and the controller controls the positive buffer circuit and the negative buffer circuit for driving two adjacent pixels, which are located in the same column but different rows on the LCD panel corresponding to two successive triggers of the horizontal synchronization signal, with voltages of opposite polarities when the detector detects that two states of the polarity signal at two successive triggers of the horizontal synchronization signal differ.
14. The driving circuit of claim 13 wherein the pixel to he driven with a positive voltage is precharged to a predetermined positive level before being driven, and the pixel to be driven with a negative voltage is precharged to a predetermined negative level before being driven.
15. The driving circuit of claim 14 wherein the positive buffer circuit comprises a first precharge circuit for providing the predetermined positive level, and the negative buffer circuit comprises a second precharge circuit for providing the predetermined negative level.
16. The driving circuit of claim 15 wherein the first precharge circuit and the second precharge circuit are source followers.
17. The driving circuit of claim 13 wherein each of the positive buffer circuit and the negative buffer circuit comprises a class-A operational amplifier buffer for driving the pixels.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for adjusting an oscillator (44) in a system, the system comprising an adjustable oscillator (44), a time source (31) knowing a clock time with a specified accuracy, and a packet switched network (21) between the oscillator and said time source, the method comprising:
updating a clock (42) on the basis of the clock time known to said time source (31) over the packet switched network (21), the clock being on the same side of the packet switched network as the adjustable oscillator (44):
using said clock (42) in the adjustment of the oscillator (44) for adjusting the oscillator to oscillate at a desired frequency.
2. A method according to claim 1, the method comprising:
counting pulses generated by the oscillator (44) during a counting period for producing oscillator control information, which counting period starts at a determined first time instant and ends at a determined second time instant, said time instants being determined on the basis of the clock time of said clock (42);
adjusting the oscillator (44) to oscillate at the desired frequency using said control information.
3. A method according to claim 2, the method comprising:
determining the reliability of the clock time of said clock (42) at said time instants, whereby in the case where the clock time at said first time instant is not reliable, starting of the counting period is delayed with a specified first delay, and in a case where the clock time at said second time instant is not reliable, ending of the counting period is delayed with a specified second delay.
4. A method according to claim 2, wherein NTP (Network Timing Protocol) adjustment is used in updating the clock time of said clock (42) and said first and second time instants are scheduled for a point in time immediately upon performing the NTP adjustment of the clock (42).
5. A method according to claim 2, wherein said clock (42) is located in the NTP client or in connection therewith, and said time source is an NTP server (31) and in the method:
the NTP client inquires and receives from the NTP server (31) a clock time having an accuracy of NTP over the packet switched network (21);
the clock time of said clock (42) is compared in the NTP client with the received clock time having the accuracy of NTP for obtaining an offset value;
the clock time of said clock (42) is adjusted according to NTP on the basis of the offset value;
data on the offset values are maintained in the memory of the system, and
the reliability of the clock time of said clock (42) at any of said time instants is determined by comparing the offset value used at least in one NTP adjustment of the clock (42) preceding said time instant with a specified condition.
6. A method according to claim 5, wherein offset values used in more than one NTP adjustment of the clock (42) preceding said time instant are compared with a specified condition, which specified condition is that all offset values to be compared are lower than a specified limit value set to the offset value and that none of the offset values to be compared is missing.
7. A method according to claim 1, wherein said clock (42) is located in the NTP client or in connection therewith, and said time source is the NTP server (31) and in the method
the NTP client inquires and receives from the NTP server (31) a clock time having an accuracy of NTP over the packet switched network (21);
in the NTP client, the clock time of said clock (42) is compared with the received clock time having the accuracy of NTP for obtaining an offset value;
data on the offset values are maintained in the memory of the system;
the reliability of the offset value is determined;
said oscillator (44) is adjusted on the basis of said offset value in the case where the offset value is reliable, and
the oscillating frequency of the oscillator (44) is derivedapplied () for the reference frequency of said clock (42) for updating the clock (42).
8. A method according to claim 7, wherein the reliability of the offset value is determined by comparing said offset value with a moving average of the offset values which is calculated from a specified set of offset values preceding said offset value.
9. An apparatus for adjusting an oscillator in a system, the system comprising an adjustable oscillator (44), a time source (31) knowing a clock time with a given accuracy and a packet switched network (21) between the oscillator and said time source, the apparatus comprising:
a clock (42) which is on the same side of the packet switched network (21) as the adjustable oscillator (44);
updating means (41) for updating the clock (42) over the packet switched network (21) on the basis of the clock time known to said time source (31);
adjusting means (45, 51 to 57, 64, 67, DAC) for adjusting the oscillator (44) to oscillate at a desired frequency by means of said clock (42).
10. Computer software for adjusting the oscillator in a system comprising an adjustable oscillator (44), a time source (31) which knows a clock time with a given accuracy and a packet switched network (21) between the oscillator and said time source, the software comprising a program code for:
updating the clock (42) over the packet switched network (21) on the basis of the clock time known to the time source (31), the clock being on the same side of the packet switched network (21) as the adjustable oscillator (44);
using said clock (42) in the adjustment of the oscillator (44) for adjusting the oscillator to oscillate at a desired frequency.