1. A tray for a semiconductors comprising:
a tray portion having a top horizontal planar surface and a bottom horizontal planar surface, wherein the top horizontal planar surface has a plurality of chip recesses arranged in a matrix formed therein, said chip recesses positioned above the bottom planar surface;
a rail portion extending substantially around the tray portion and offset downwardly from the top tray portion, wherein the rail portion has a top horizontal planar surface and a bottom horizontal planar surface; and
an intermediate portion interconnecting the tray portion and the rail portion, wherein the intermediate portion has an outwardly facing surface and an inwardly facing surface, wherein the outwardly facing surface has four planar faces one at each side of the tray, wherein each planar face of the outwardly facing surface extends from the top horizontal planar surface of the tray portion to the top horizontal planar surface of the rail portion, and wherein each of the four planar faces of the outwardly facing surface is oriented at an angle of more than 115\xb0 with respect to the rail portion, wherein each of the inwardly facing surfaces has four inward planar faces, each of which extends from the bottom horizontal planar surface of the tray portion to the rail portion and wherein the bottom horizontal surface of the tray portion is generally aligned with the top horizontal surface of the rail portion.
2. The tray of claim 1, wherein the intermediate portion is oriented at an angle of between 115\xb0 and 150\xb0 with respect to the rail portion.
3. The tray of claim 1, wherein the rail portion has a plurality of reduced thickness regions, wherein the reduced thickness regions have a thickness that is less than 80 percent of a thickness of the rail portion.
4. The tray of claim 3, wherein the reduced thickness regions comprise more than about 33 percent of a length of the rail portion.
5. The tray of claim 1, wherein four inward planar faces of the inwardly facing surface of the intermediate portion are entirely below the plurality of chip recesses and are respectively parallel to the four planar faces of the outwardly facing surface of the intermediate portion.
6. The tray of claim 1, and further comprising at least one nub extending from a lower surface of the tray portion, wherein the at least one nub enables the tray to be used with a jig that is designed for use with a differently sized tray.
7. The tray of claim 1, wherein an upper surface of the tray portion is higher than an upper surface of the intermediate portion and wherein the upper surface of the intermediate portion is higher than an upper surface of the rail portion.
8. A system for storing semiconductors comprising:
a first chip tray comprising a first tray portion, a first rail portion and a first intermediate portion all integral with one another, wherein the first tray portion has a top planar surface and a bottom planar surface, wherein the top planar surface has a plurality of chip recesses arranged in a matrix formed therein, wherein the first rail portion extends substantially around the first tray portion and is offset downwardly from the first tray portion, wherein the first rail portion has a top planar surface and a bottom planar surface, wherein the first intermediate portion interconnects the first tray portion and the first rail portion, wherein the first intermediate portion has an outwardly facing surface and an inwardly facing surface, wherein the outwardly facing surface has four first planar faces, wherein each first planar face extends from the top planar surface of the first tray portion to the top planar surface of the first rail portion, wherein each first planar face is oriented at an angle of more than 115\xb0 with respect to the top planar surface of the rail portion, and wherein a lower surface the bottom planar surface of the first tray portion, the first intermediate portion and the first rail portion define a recess and wherein the bottom horizontal surface of the tray portion is generally aligned with the top horizontal surface of the rail portion; and
a second chip tray comprising a second tray portion, a second rail portion and a second intermediate portion, wherein the second rail portion extends substantially around the second tray portion, wherein the second intermediate portion interconnects the second tray portion and the second rail portion, and wherein the second intermediate portion is oriented at an angle of more than 115\xb0 with respect to the rail portion, wherein the second tray portion seats in the recess to retain semiconductors in desired positions on the second tray portion so that an upper surface of the second tray portion is proximate a lower surface of the first tray portion.
9. The system of claim 8, wherein the first and second rail portions each have a plurality of reduced thickness regions, wherein the reduced thickness regions have a thickness that is less than 80 percent of a thickness of the first and second rail portions.
10. The system of claim 8, wherein the first and second tray each have a length and a width that are both greater than about 3.5 inches.
11. The system of claim 10, wherein upper surfaces of the first and second tray portions each have a deviation in height of less than 0.004 inches.
12. A system for storing semiconductors comprising:
a first chip tray comprising a first tray portion, a first rail portion and a first intermediate portion all integral with one another, wherein the first tray portion has a top planar surface and a bottom planar surface, wherein the top planar surface has a plurality of chip recesses arranged in a matrix formed therein, wherein the first rail portion extends substantially around the first tray portion and is offset downwardly from the first tray portion, wherein the first rail portion has a top planar surface and a bottom planar surface, wherein the first intermediate portion interconnects the first tray portion and the first rail portion, wherein the first intermediate portion has an outwardly facing surface and an inwardly facing surface, wherein the outwardly facing surface has four first planar faces, wherein each first planar face extends from the top planar surface of the first tray portion to the top planar surface of the first rail portion, wherein each first planar face is oriented at an angle of more than 115\xb0 with respect to the top planar surface of the rail portion, and wherein a lower surface the bottom planar surface of the first tray portion, the first intermediate portion and the first rail portion define a recess;
a second chip tray comprising a second tray portion, a second rail portion and a second intermediate portion, wherein the second rail portion extends substantially around the second tray portion, wherein the second intermediate portion interconnects the second tray portion and the second rail portion, and wherein the second intermediate portion is oriented at an angle of more than 115\xb0 with respect to the rail portion, wherein the second tray portion seats in the recess to retain semiconductors in desired positions on the second tray portion so that an upper surface of the second tray portion is proximate a lower surface of the first tray portion; and
a spring box having a recess formed therein that is adapted to receive the first and second chip trays and maintain the first and second chip trays at a substantially stationary position therein.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A card processing apparatus having a first transport path extended from a card supply unit, a turning unit on said first transport path, a first processing unit to perform the determined process on a card on said first transport path, a second transport path established obliquely to the card transport direction transported through said first transport path based on said turning unit having an angle of 90 or more and less than 180 with regard to the transport path extending from said first processing unit on said first transport path up to said turning unit, a second processing unit to perform the determined process on said card on said second transport path, and a card discharge unit provided at the end of either said first or said second transport paths.
2. The card processing apparatus according to claim 1, wherein said first processing unit and said second processing unit are incorporated into one casing.
3. The card processing apparatus according to claim 1, wherein said first processing unit and said second processing unit each incorporated into independent, interlockable casings.
4. The card processing apparatus according to claim 1, wherein said card discharge unit established at the end of said first transport path, said turning unit transports said card to said second processing unit, receives said card processed at said second processing unit from said second processing unit and sends said card to said discharge unit.
5. The card processing apparatus according to claim 1, wherein said card discharge unit established at the end of said second transport path wherein said cards processed by said second processing unit sent to said discharge unit along the same direction as the transport of said card to said second processing unit from said turning unit.
6. The card processing apparatus according to claim 2, wherein either said first processing unit or said second processing unit is a thermal transfer printer and the other is a film coating unit.
7. The card processing apparatus according to claim 3, wherein either said first processing unit or said second processing unit is a thermal transfer printer and the other is a film coating unit.
8. A card processing apparatus provided with a first transport path extended from a card supply unit, a turning unit established along said first transport path, a second transport path and a third transport path established obliquely to said first transport path based on said turning unit, a card discharge unit provided at the end of at least one of said first, said second and said third transport paths, and first, second and third processing units each established in said first, said second and said third transport paths to perform the determined processes on a card.
9. The card processing apparatus according to claim 8, wherein said second processing unit and said third processing arranged obliquely in directions going away based on said turning unit.
10. The card processing apparatus according to claim 8, wherein said second processing unit and said third processing are arranged in a different level from said first processing unit.
11. The card processing apparatus according to claim 8, wherein said first processing unit, said second processing unit and said third processing unit are incorporated into one casing.
12. The card processing apparatus according to claim 8, wherein at least one of said first processing unit, said second processing unit or said third processing unit is incorporated into a casing that is separate and independent from other said processing units and is interlockable to casing storing other said processing units.
13. The card processing apparatus according to claim 11, wherein at least one of said first processing unit, said second processing unit and said third processing unit is a thermal transfer printer.
14. The card processing apparatus according to claim 12, wherein at least one of said first processing unit, said second processing unit and said third processing unit is a thermal transfer printer.
15. The card processing apparatus according to claim 11, wherein said first processing unit, said second processing unit and said third processing unit could be thermal transfer printers, film coating units or magnetic encoders.
16. The card processing apparatus according to claim 12, wherein said first processing unit, said second processing unit and said third processing unit could be thermal transfer printers, film coating units or magnetic encoders.