1. A nonvolatile charge trap memory device, comprising:
a substrate having a channel region, a source region and a drain region; and
a gate stack disposed above the substrate, over the channel region, wherein the gate stack comprises:
a tunnel dielectric layer disposed above the channel region;
a first charge-trapping region and a second charge-trapping region, the regions disposed above the tunnel dielectric layer and separated by a distance;
an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region;
a gate dielectric layer disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer; and
a gate electrode disposed above the gate dielectric layer.
2. The nonvolatile charge trap memory device of claim 1, wherein the isolating dielectric layer both physically and electrically isolates the first charge-trapping region from the second charge-trapping region.
3. The nonvolatile charge trap memory device of claim 1, wherein the distance between the first charge-trapping region and the second charge-trapping region is approximately in the range of 3-20 nanometers.
4. The nonvolatile charge trap memory device of claim 1, wherein the isolating dielectric layer comprises silicon oxide or silicon dioxide.
5. The nonvolatile charge trap memory device of claim 1, wherein the gate dielectric layer comprises a high-k dielectric material.
6. The nonvolatile charge trap memory device of claim 1, wherein the gate electrode is a metal gate electrode.
7. The nonvolatile charge trap memory device of claim 1, wherein the nonvolatile charge trap memory device is a SONOS-type device.
8. The nonvolatile charge trap memory device of claim 7, wherein the source region, the drain region and the gate electrode are N-type, and the SONOS-type device is an N-type SONOS-type device.
9. A nonvolatile charge trap memory device, comprising:
a substrate having a channel region, a source region and a drain region; and
a gate stack disposed above the substrate, over the channel region, wherein the gate stack comprises:
a first tunnel dielectric layer region and a second tunnel dielectric layer region disposed above the channel region and separated by a distance;
a first charge-trapping region and a second charge-trapping region, the regions disposed above the first tunnel dielectric layer region and second tunnel dielectric layer region, respectively, and separated by the distance;
an isolating dielectric layer disposed above the channel region, between the first charge-trapping region and the second charge-trapping region, and between the first tunnel dielectric layer region and the second tunnel dielectric layer region;
a gate dielectric layer disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer; and
a gate electrode disposed above the gate dielectric layer.
10. The nonvolatile charge trap memory device of claim 9, wherein the isolating dielectric layer both physically and electrically isolates the first charge-trapping region from the second charge-trapping region.
11. The nonvolatile charge trap memory device of claim 9, wherein the distance between the first charge-trapping region and the second charge-trapping region is approximately in the range of 3-20 nanometers.
12. The nonvolatile charge trap memory device of claim 9, wherein the isolating dielectric layer comprises silicon oxide or silicon dioxide.
13. The nonvolatile charge trap memory device of claim 9, wherein the gate dielectric layer comprises a high-k dielectric material.
14. The nonvolatile charge trap memory device of claim 9, wherein the gate electrode is a metal gate electrode.
15. The nonvolatile charge trap memory device of claim 9, wherein the nonvolatile charge trap memory device is a SONOS-type device.
16. The nonvolatile charge trap memory device of claim 15, wherein the source region, the drain region and the gate electrode are N-type, and the SONOS-type device is an N-type SONOS-type device.
17. The nonvolatile charge trap memory device of claim 9, wherein the first tunnel dielectric layer region further extends along an outer sidewall of the first charge-trapping region, and the second tunnel dielectric layer region further extends along an outer sidewall of the second charge-trapping region.
18. A method of fabricating a nonvolatile charge trap memory device, the method comprising:
removing a dummy gate electrode to form a trench above a substrate having a channel region, a source region and a drain region all self-aligned to the trench;
forming a tunnel dielectric layer in the trench;
forming a first charge-trapping region and a second charge-trapping region above the tunnel dielectric layer and separated by a distance;
forming an isolating dielectric layer between the first charge-trapping region and the second charge-trapping region;
forming a gate dielectric layer above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer; and
forming a gate electrode disposed above the gate dielectric layer.
19. The method of claim 18, wherein forming the isolating dielectric layer further comprises forming the isolating dielectric layer above the tunnel dielectric layer.
20. The method of claim 18, wherein forming the isolating dielectric layer further comprises forming the isolating dielectric layer between first and second regions of the tunnel dielectric layer.
21. The method of claim 18, wherein forming the isolating dielectric layer comprises both physically and electrically isolating the first charge-trapping region from the second charge-trapping region.
22. The method of claim 18, wherein forming the isolating dielectric layer comprises forming a silicon oxide or silicon dioxide layer.
23. The method of claim 18, wherein forming the gate dielectric layer comprises forming a high-k dielectric material.
24. The method of claim 18, wherein forming the gate electrode comprises forming a metal gate electrode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A sample conveying method using a conveying means having a conveying robot which conveys a sample in atmosphere between a lock chamber located at the entrance of a vacuum chamber and a cassette which accommodates a plurality of samples;
separately conveying each cassette in said plurality of cassettes horizontally to a position where a conveyed cassette faces to said conveying robot,
holding said sample by a scooping device equipped on said conveying robot which is anchored at a position adjacent said cassette and said lock chamber using a vacuum adhering and vertically moving said sample for a predetermined amount, and
moving said scooping device between said cassette and said lock chamber.