1. A method for testing a core power distribution system for an integrated circuit chip comprising:
arranging a plurality of experiments for an integrated circuit chip, the arranging the plurality of experiments for the integrated circuit chip including progressively depopulating pins of the integrated circuit chip;
performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
generating a schmoo diagram for each of the plurality of experiments; and
analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
2. The method for testing a core power distribution system of claim 1 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.
3. The method for testing a core power distribution system of claim 1 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.
4. The method for testing a core power distribution system of claim 1 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.
5. The method for testing a core power distribution system of claim 1 further comprising:
repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
generating a schmoo diagram for each of the repeated plurality of experiments; and
analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
6. A method for testing a core power distribution system for an integrated circuit chip comprising:
arranging a plurality of experiments for an integrated circuit chip;
performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
generating a schmoo diagram for each of the plurality of experiments; and
analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the arranging a plurality of experiments for an integrated circuit chip includes at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.
7. A system for testing a core power distribution system for an integrated circuit chip comprising:
means for arranging a plurality of experiments for an integrated circuit chip, the means for arranging the plurality of experiments for the integrated circuit chip includes progressively depopulating pins of the integrated circuit chip;
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
8. The system for testing a core power distribution system of claim 7 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.
9. The system for testing a core power distribution system of claim 7 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.
10. The system for testing a core power distribution system of claim 7 wherein
the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.
11. The system for testing a core power distribution system of claim 7 further comprising:
means for repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the repeated plurality of experiments; and,
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
12. A system for testing a core power distribution system for an integrated circuit chip comprising:
means for arranging a plurality of experiments for an integrated circuit chip;
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the means for arranging a plurality of experiments for an integrated circuit chip includes at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.
13. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.
14. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.
15. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.
16. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:
means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency;
wherein the plurality of experiments for an integrated circuit chip include at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.
17. The apparatus for testing a core power distribution system of claim 16 further comprising:
means for repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;
means for generating a schmoo diagram for each of the repeated plurality of experiments; and
means for analyzing the schmoo diagrams to determine whether the core power distribution system functions are acceptable at a particular frequency.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-10. (canceled)
11. A method for classifying defects, comprising:
calculating feature quantities of defect image which is obtained by imaging a defect on a sample;
classifying said defect image into one of categories by using information on said calculated feature quantities;
displaying said classified defect image in a region on a display screen which is defined to said classified category;
adding classification information on said classified category to said displayed defect image;
in the event of a need to reclassify, moving classification of said displayed defect image which is added said information on said classified category to one of the other categories; and
changing information of said added classified information to new information on said one of the other categories.
12. A method for classifying defects according to the claim 11, wherein said display screen is screen of a PC, and in the moving said displayed image is moved from said region on said display screen of said PC which is defined to said classified category to said region on said display screen which is defined to said one of the other categories by drag and drop operation by a mouse of said PC.
13. A method for classifying defects according to the claim 11, wherein in the calculating, said feature quantities includes a size, color and shape of said defect image.
14. A method for classifying defects, comprising:
displaying a defect image in a region on a display screen which is defined to one of a predetermined category and adding information on one of said predetermined categories to said displayed defect; and
in the even of a need to reclassify, changing information from said added information on one of said predetermined categories to a new information on one of the other predetermined categories by moving said defect image from said region defined to said one of the predetermined category to a region on said display screen which is defined to said one of the other predetermined categories.
15. A method for classifying defects according to the claim 14, wherein said display screen is screen of a PC, and in the changing information, said displayed image is moved from said region on said display screen of said PC which is defined to said one of the predetermined categories to said region on said display screen which is defined to said one of the other predetermined categories by drag and drop operation by a mouse of said PC.
16. A method for classifying defects according to the claim 14, wherein said information includes features of said defect image which is not changed by moving said defect image from said region defined to said one of the predetermined category to a region on said display screen which is defined to said one of the other predetermined categories.
17. A method for classifying defects according to the claim 16, wherein said information on features of said defect image includes a size, color and shape of said defect image.
18. An apparatus for classifying defect, comprising:
a feature quantity calculating unit which calculates a feature quantity of a defect image obtained by imaging a defect on a specimen;
a memory which stores said calculated feature quantity in relation with said defect image;
a defect classifying unit which classifies said defect image stored in said memory into a classified category selected from a plurality of predetermined categories by using information on said calculated feature quantity and stores information on said calculated category of the predetermined categories;
a display which has a screen on which said classified defect image is displayed in a region defined to said classified category of the predetermined categories;
a moving unit which, in the event of a need to reclassify, moves said displayed defect image from said region defined to said classified category of the predetermined categories to a region defined to one of the other predetermined categories on said screen; and
a category information rewriting unit which rewrites category information on said defect image stored in said memory from said classified category of the predetermined categories to said one of the other predetermined categories.
19. An apparatus for classifying defects according to the claim 18, wherein said-display is a display of a PC, and said moving unit includes a mouse of said PC.
20. An apparatus for classifying defects according to the claim 18, wherein said memory stores said calculated feature quantity including a size, color and shape of said defect image.