1. A machine implemented method at a debug host device, the method comprising:
accessing, via a hardware integrated debug framework, data in volatile random access memory of a debug target device;
accessing, via the hardware integrated debug framework, data in nonvolatile random access electrically erasable semiconductor memory of the debug target device;
accessing, via the hardware integrated debug framework, one or more registers of one or more processors on the debug target device; and
creating, on the debug host device, a debug target system snapshot comprising the volatile memory data, nonvolatile memory data, and data from one or more registers of one or more processors on the debug target device, wherein the debug target device has malfunctioned due to a failure.
2. The machine implemented method as in claim, 1 wherein accessing data in volatile memory of a debug target device comprises:
accessing, through an external debug interface, the hardware integrated debug framework;
copying, via the hardware integrated debug framework, one or more page tables on one or more processors from the debug target device to the debug host device, through the external debug interface;
accessing one or more physical memory addresses on the debug target device using virtual memory mappings listed in one or more page tables copied from one or more processors on the debug target device; and
copying, to the debug host device, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.
3. The machine implemented method as in claim 2, wherein the hardware integrated debug framework is accessed through an external debug interface by a hardware debug device coupled to the external debug interface and the debug host device, and wherein the accessing occurs by the debug host device pulling the data from the debug target device.
4. The machine implemented method as in claim 1, wherein accessing data in nonvolatile electronically erasable semiconductor memory on a debug target device comprises:
accessing, via the hardware integrated debug framework, the input and output pins of the electrically erasable semiconductor memory;
accessing, via the input and output pins of the electrically erasable semiconductor memory, one or more stored data blocks; and
copying, through the external debug interface, one or more data blocks from the electrically erasable semiconductor memory to the debug host device.
5. The machine implemented method as in claim 4, wherein the input and output pins of the electrically erasable semiconductor memory device are accessed via a general-purpose input-output controller using the command protocol of the semiconductor memory device.
6. The machine implemented method as in claim 5, wherein the general-purpose input-output controller is commanded by a memory controller device programmed with the command protocol of the electrically erasable semiconductor memory.
7. The machine implemented method as in claim 6, wherein the memory controller device for the electronically erasable semiconductor memory is controlled by a direct memory access controller, wherein the direct memory access controller is controlled via the hardware integrated debug framework.
8. A machine implemented method at a debug host device, the method comprising:
accessing, through an external debug interface on a debug target device, a hardware integrated debug framework of a system on a chip integrated circuit;
copying, via the hardware integrated debug framework, a page table on one or more processors from the debug target device, to the debug host device, through the external debug interface;
analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations;
accessing, via the debug framework, one or more physical memory addresses containing kernel memory allocations on the debug target device; and
copying, through the debug interface, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.
9. The machine implemented method as in claim 8, wherein analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations comprises applying an algorithm to the set of page mapped virtual addresses to find a pattern of mappings that indicate one or more kernel memory allocations.
10. The machine implemented method as in claim 8, wherein analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations further comprises reading a bit in the page table entry data structure.
11. A non-transitory machine-readable storage medium having instructions stored therein, which when executed by a machine cause the machine to perform operations, the operations comprising:
accessing data in the volatile random access system memory of a debug target device via a hardware integrated debug framework;
accessing data on a nonvolatile random access electrically erasable semiconductor memory device of the debug target device via the hardware integrated debug framework;
accessing one or more registers of one or more processors on the debug target device; and
creating a debug target system snapshot on a debug host device, the debug target system snapshot comprising at least the system memory data, the nonvolatile memory data, and the data from one or more registers of one or more processors on the debug target device, wherein the debug target device has malfunctioned due to a failure.
12. The machine-readable storage of claim 11, wherein accessing data in system memory of a debug target device comprises:
accessing the hardware integrated debug framework through an external debug interface;
copying, to the debug host device, one or more page tables from on one or more processors on the debug target device using the hardware integrated debug framework;
accessing one or more physical memory addresses on the debug target device using virtual memory mappings listed in one or more page tables copied from one or more processors on the debug target device; and
copying, to the debug host device, one or more blocks of memory stored at the one or more physical system memory addresses on the debug target device.
13. The machine-readable storage of claim 11, wherein accessing data in nonvolatile electrically erasable semiconductor memory on a debug target device comprises:
accessing, via the hardware integrated debug framework, the input and output pins of the electrically erasable semiconductor memory;
reading one or more data blocks from the electrically erasable semiconductor memory using a command protocol specific to the electrically erasable semiconductor memory device; and
copying, through the debug interface, one or more blocks of data stored on the electrically erasable semiconductor memory of the debug target device, to the debug host device, using the command protocol of the electrically erasable semiconductor memory device.
14. The machine readable storage of claim 13, wherein the input and output pins of the nonvolatile electronically erasable semiconductor memory device are driven via a general purpose input-output controller, which is controlled via the hardware integrated debug framework.
15. The machine readable storage of claim 14, wherein the general purpose input-output controller is commanded by a memory controller device specific to the nonvolatile electronically erasable semiconductor memory, and wherein the memory controller device is controlled by a hardware debugger using the hardware integrated debug framework.
16. The machine readable storage of claim 15, wherein the memory controller device for the electronically erasable semiconductor memory is controlled by a direct memory access controller, wherein the direct memory access controller is controlled via the hardware integrated debug framework.
17. A non-transitory machine-readable storage medium having instructions stored therein, which when executed by a machine cause the machine to perform operations, the operations comprising:
accessing, through an external debug interface, a hardware integrated debug framework;
copying, via the hardware integrated debug framework, a page table on one or more processors from the debug target device to the debug host device, through the external debug interface;
analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations by applying an algorithm to the set of page mapped virtual addresses, the algorithm comprising analyzing the set of page mapped virtual addresses to find a pattern of mappings, the pattern of mappings to indicate the presence of one or more kernel memory allocations.
accessing, via the debug framework, one or more physical memory addresses containing kernel memory allocations on the debug target device; and
copying, through the debug interface, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.
18. The machine readable storage of claim 17, wherein analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations further comprises reading a bit in the page table entry data structure.
19. A debugging system for embedded devices, the system comprising:
a debug host device comprising one or more processors, a main system memory, and a nonvolatile storage device;
a hardware debug device coupled with the debug host device, the hardware debug device to provide a debug interface between a debug host device and one or more debug target devices;
a debug target device comprising a system on a chip integrated circuit, volatile DRAM memory, and nonvolatile electrically erasable semiconductor memory, wherein the system on a chip integrated circuit comprises one or more processors and a hardware integrated debug framework, the hardware integrated debug framework to allow the hardware debug device and debug host device to control the one or more processors of the system on a chip integrated circuit after the debug target device malfunctions due to an operating system level failure; and
a debug console, attached to the debug host device, to monitor debug output from the debug target device.
20. The system as in claim 19, wherein the debug target device further comprises a general purpose input-output controller, to control the input and output pins of the nonvolatile electronically erasable semiconductor memory device.
21. The system as in claim 20, wherein the debug host device is coupled to the debug target device through at least one network.
22. The system as in claim 20, wherein the general-purpose input-output controller is controlled by a semiconductor memory controller device, the semiconductor memory device controlled via the hardware integrated debug framework.
23. The system as in claim 22, wherein the semiconductor memory controller device is controlled by a direct memory access controller, the direct memory access controller controlled by the debug host device via the hardware integrated debug framework.
24. The system as in claim 23, wherein the debug host device uses a device driver stored in system memory to control hardware on the debug target device via the hardware integrated debug framework.
25. The system as in claim 23, wherein a software simulation of one or more hardware components on the debug target device substitutes for one or more components of the debug target device.
26. The system as in claim 23, wherein external hardware that duplicates the functionality of one or more internal hardware components of the debug target device substitutes for one or more components of the debug target device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of identifying a connection error when a first module is electrically connected to a plurality of second modules, said method comprising the steps of:
distinguishing said second modules connected to said first module;
determining whether said distinguished second modules are preliminarily registered or not; and
judging that there is a connection error if said distinguished second modules are not preliminarily registered;
wherein each of said steps is carried out by one of the modules selected from the group consisting of said first module and said plurality of second modules.
2. The method of claim 1 wherein said first module has a plurality of connectors, each of said second modules being mounted to a corresponding different one of said connectors, wherein said second modules are preliminarily registered for each of said connectors, and wherein said step of judging comprises judging for each of said connectors whether said distinguished second module is not preliminarily registered.
3. The method of claim 2 wherein a plurality of second modules are preliminarily registered as a combination corresponding to a plurality of said connectors and wherein said step of judging comprises judging whether or not the distinguished second modules are preliminarily registered as said combination.
4. The method of claim 1 wherein said step of judging comprises judging a connection error also if a module cannot be distinguished in said step of distinguishing.
5. The method of claim 1 further comprising the step of making a report when it is judged in said step of judging that there is a connection error.
6. An electronic apparatus comprising:
a first module having a plurality of connectors;
a plurality of second modules each connected to said first module through a different one of said connectors;
a registration part where a plurality of types of second modules are preliminarily registered;
a distinguishing part for distinguishing second modules connected to said connectors;
a determining part for determining whether the distinguished second modules are of a type preliminarily registered in said registration part; and
a judging part for judging that there is a connection error of said second module if said distinguished second modules are determined to be not registered in said registration part.
7. The electronic apparatus of claim 6 wherein said types of second modules are registered corresponding to each of said connectors and wherein said determining part determines whether the distinguished second modules are each of a type preliminarily registered corresponding to each of said connectors.
8. The electronic apparatus of claim 7 wherein said types of second modules are preliminarily registered in said registration part as combinations corresponding to said connectors and said determining part determines whether or not the distinguished second modules are preliminarily registered as one of said combinations.
9. The electronic apparatus of claim 6 wherein said judging part judges that there is a connection error also when said distinguishing part fails to distinguish said second module.
10. The electronic apparatus of claim 6 further comprising a reporting part for making a report when said judging part judges that there is a connection error.
11. The electronic apparatus of claim 6 further comprising a limiting part that limits at least a portion of operations by said electronic apparatus when said judging part judges that there is connection error.
12. The electronic apparatus of claim 6 wherein said first module comprises a base substrate having common wiring that is connected to each of said connectors, said second modules each comprising a mounting substrate having a dedicated circuit corresponding to a specified function, said dedicated circuit becoming connected to said common wiring as said mounting substrate is connected to said connector, said second modules each further comprising a control circuit which is mounted either to said base substrate or to said mounting board and is connected to said common wiring, said control circuit including at least said distinguishing part, said determining part and said judging part, said control circuit serving to identify said mounting board connected to said connector of said base substrate and to function accordingly as a specified one of a plurality of types of apparatus.