1. A method, comprising:
providing a substrate having a plurality of conductive pads;
placing a plurality of semiconductor dies on the plurality of conductive pads;
placing a mold device on the substrate, the mold device having a plurality of recesses, wherein the placing the mold device includes covering each of the semiconductor dies by a respective one of the recesses; and
thereafter bonding the semiconductor dies to the conductive pads.
2. The method of claim 1, wherein the placing the mold device substantially restricts movement of the semiconductor dies that are covered by recesses in the mold device.
3. The method of claim 2, wherein the placing the mold device includes restricting a movement range of each semiconductor die covered by the recess to be less than about 5 microns in any lateral direction.
4. The method of claim 1, wherein the placing the mold device includes securing the mold device with respect to the substrate, so that the mold device is substantially free of lateral movement with respect to the substrate.
5. The method of claim 1, wherein the placing the mold device includes applying pressure to the semiconductor dies through the mold device.
6. The method of claim 1, wherein the recesses each have a sloped profile.
7. The method of claim 1, wherein the bonding includes heating the substrate, the semiconductor dies, and the mold device in a reflow oven.
8. The method of claim 1, further including:
applying a flux material on each of the conductive pads before the semiconductor dies are placed on the conductive pads; and
aligning each of the recesses of the mold device with a respective one of the semiconductor dies before the mold device is placed on the substrate.
9. The method of claim 1, wherein the semiconductor dies include light-emitting diode (LED) devices.
10. A method of fabricating a photonic device, comprising:
providing a wafer having a plurality of bonding pads disposed thereon;
positioning a plurality of photonic devices on the plurality of bonding pads, respectively;
covering the photonic devices with a mold fixture having a plurality of concave openings, wherein each photonic device is secured by a respective one of the concave openings, and wherein a lateral shift between each photonic device and the respective bonding pad therebelow is less than a predefined value; and
bonding the photonic devices to the bonding pads while the photonic devices are covered by the mold fixture, wherein the bonding is carried out at least in part through a thermal process.
11. The method of claim 10, wherein the predefined value is about 10 microns.
12. The method of claim 10, wherein the covering includes securing the mold fixture such that the mold fixture is substantially free of lateral shift with respect to the wafer.
13. The method of claim 10, further including: applying a tunable amount of pressure through the mold fixture to each of the photonic devices.
14. The method of claim 10, wherein the concave openings each have a tapered cross-sectional profile.
15. The method of claim 10, further including:
before the positioning, applying a flux material on each of the bonding pads so that the photonic devices are coupled to the bonding pads through the flux material; and
before the covering, aligning the mold fixture with the wafer so that each concave opening is substantially aligned with a respective one of the photonic devices.
16. A method of light-emitting diode (LED) packaging, comprising:
providing a sub-mount having a plurality of bonding pads disposed thereon;
coupling a plurality of LED dies to the plurality of bonding pads, wherein each LED die is coupled to a respective one of the bonding pads;
providing a mold apparatus, the mold apparatus including a plurality of concave recesses;
placing the mold apparatus over the sub-mount, wherein each LED die is housed in a respective one of the recesses; and
thereafter heating the sub-mount, the LED dies, and the mold apparatus in a thermal reflow process, thereby causing the LED dies to be bonded to the bonding pads, respectively;
wherein each recess substantially restricts a positional shift of the LED die below with respect to the bonding pad coupled thereto during the heating.
17. The method of claim 16, wherein the placing the mold apparatus includes positionally securing the mold apparatus relative to the sub-mount.
18. The method of claim 16, wherein the placing the mold apparatus includes applying a predetermined amount of pressure to the LED dies through the mold apparatus.
19. The method of claim 16, wherein the placing the mold apparatus includes aligning the recesses with the LED dies through an optical positioning process.
20. The method of claim 16, wherein the recesses of the mold apparatus each have a non-uniform cross-sectional profile.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus comprising:
a front end to receive an instruction indicating a source and a destination, the source having a first plurality of packed floating point values, the first plurality of the packed floating point values including a first floating point value, a second floating point value, and a third floating point value, the second floating point value between the first floating point value and the third floating point value; and
an execution core coupled with the front end, the execution core to store a result corresponding to the instruction in the destination, the result including a second plurality of packed floating point values, the second plurality of the packed floating point values including is fourth floating point value that is equal to the first floating point value, a fifth floating point value, that is equal to the first floating point value, a sixth floating point value that is equal to the third floating point value, and a seventh floating point value that is equal to the third floating point value,
wherein the fourth and fifth floating point values being equal to the first floating point value is fixed by a type of the instruction.
2. The apparatus of claim 1, wherein the instruction does not explicitly specify that the fourth and fifth floating point values are to be equal to the first floating point value.
3. The apparatus of claim 1, wherein an op code of the instruction indicates that the fourth and fifth floating point values are to be equal to the first floating point value.
4. The apparatus of claim 1, wherein the instruction indicates a single source operand.
5. The apparatus of claim 1, wherein the source comprises one of a 128-bit memory location and a 128-bit register.
6. The apparatus of claim 1, wherein the core is to duplicate the first floating point value of the source as a result of the instruction.
7. An apparatus comprising;
a front end to receive an instruction indicating a single source and a destination, the source including a first plurality of packed single precision floating point values, the first plurality of the packed single precision floating point values including a first single precision floating point value in bits 31-0 of the source, a second single precision floating point value in bits 63-32 of the source, a third single precision floating point value in bits 95-64 of the source, and a fourth single precision floating point value in bits 127-96 of the source; and
an execution core coupled with the front end, the execution core to store a packed result corresponding to the instruction in the destination indicated by the instruction, the packed result including a second plurality of packed single precision floating point values, the second plurality of the packed single precision floating point values including a fifth single precision floating point value in bits 31-0 of the packed result that is equal to the first single precision floating point value, a sixth single precision floating point value in bits 63-32 of the packed result that is equal to the first single precision floating point value, a seventh single precision floating point value in bits 95-64 of the packed result that is equal to the third single precision floating point value, and an eighth single precision floating point value in bits 127-96 of the packed result that is equal to the third single precision floating point value,
wherein an op code of the instruction indicates that the fifth and sixth single precision floating point values are to be equal to the first single precision floating point value.
8. The apparatus of claim 7, wherein the instruction implicitly indicates that the fifth and sixth single precision floating point values are to be equal to the first single precision floating point value.
9. The apparatus of claim 7, wherein one of the fifth and the sixth single precision floating point values is a copy of the first single precision floating point value, and another of the fifth and the sixth single precision floating point values is a duplicate of the first single precision floating point value.
10. An apparatus comprising:
a front end to receive an instruction indicating a single source and a destination, the source including a first plurality of packed single precision floating point values, the first plurality of the packed single precision floating point values including a first single precision floating point value in bits 31-0 of the source, a second single precision floating point value in bits 63-32 of the source, a third single precision floating point value in bits 95-64 of the source, and a fourth single precision floating point value in bits 127-96 of the source; and
an execution core coupled with the front end, the execution core to store a packed result corresponding to the instruction in the destination indicated by the instruction, the packed result including a second plurality of packed single precision floating point values, the second plurality of the packed single precision floating point values including a fifth single precision floating point value in bits 31-0 of the packed result that is equal to the second single precision floating point value, a sixth single precision floating point value in bits 63-32 of the packed result that is equal to the second single precision floating point value, a seventh single precision floating point value in bits 95-64 of the packed result that is equal to the fourth single precision floating point value, and an eighth single precision floating point value in bits 127-96 of the packed result that is equal to the fourth single precision floating point value,
wherein the instruction implicitly indicates that the fifth and sixth single precision floating point values are to be equal to the second single precision floating point value.
11. The apparatus of claim 10, wherein an op code of the instruction indicates that the fifth and sixth single precision floating point values are to be equal to the second single precision floating point value.
12. The apparatus of claim 10, wherein one of the fifth and the sixth single precision floating point values is a copy of the second single precision floating point value, and another of the fifth and the sixth single precision floating point values is a duplicate of the second single precision floating point value.
13. The apparatus of claim 1, wherein the source comprises a memory operand.
14. The apparatus of claim 1, wherein the result has a same length as the first plurality of packed floating point values.
15. The apparatus of claim 1, wherein the second floating point value is directly between the first floating point value and the third floating point value, and wherein the source consists of four floating point values.
16. The apparatus of claim 1, wherein the result consists of the fourth, fifth, sixth, and seventh floating point values.
17. The apparatus of claim 7, wherein the source comprises a memory operand.
18. The apparatus of claim 10, wherein the source comprises a memory operand.
19. An apparatus comprising:
a decode unit to receive an instruction indicating a single source and a destination, the single source having a first plurality of packed values, the first plurality of the packed values including a first value, a second value, and a third value, the second value between the first value and the third value; and
an execution resource coupled with the decode unit, the execution resource to store a result corresponding to the instruction in the destination, the result including a second plurality of packed values, the second plurality of the packed values including a fourth value that is equal to the first value, a fifth value that is equal to the first value, a sixth value that is equal to the third value, and a seventh value that is equal to the third value,
wherein the instruction does not explicitly specify that the fourth and fifth values are to be equal to the first value.
20. The apparatus of claim 19, wherein the source comprises a memory operand.
21. The apparatus of claim 19, wherein the second floating point value is directly between the first floating point value and the third floating point value, wherein the source the source consists of four floating point values.
22. An apparatus comprising:
a decode unit to receive an instruction indicating a source and a destination, the source including a first plurality of packed single precision floating point values, the first plurality of the packed single precision floating point values including a first single precision floating point value, in bits 31-0 of the source, a second single precision floating point value in bits 63-32 of the source, a third single precision floating point value in bits 95-64 of the source, and a fourth single precision floating point value in bits 127-96 of the source; and
an execution resource coupled with the decode unit, the execution resource to store a packed result corresponding to the instruction in the destination indicated by the instruction, the packed result including a second plurality of packed single precision floating point values, the second plurality of the packed single precision floating point values including a fifth single precision floating point value in bits 31-0 of the packed result that is equal to the first single precision floating point value, a sixth single precision floating point value in bits 63-32 of the packed result that is equal to the first single precision floating point value, a seventh single precision floating point value in bits 95-64 of the packed result that is equal to the third single precision floating point value, and an eighth single precision floating point value in bits 127-96 of the packed result that is equal to the third single precision floating point value,
wherein an op code of the instruction provides that the fifth and sixth single precision floating point values are to be equal to the first single precision floating point value, and
wherein the instruction is to indicate an address of the source, and wherein the packed result is to be stored without the instruction indicating a second source having is a same address as the source.
23. An apparatus comprising:
a decode unit to receive, an instruction indicating a source and a destination, the source including a first plurality of packed single precision floating point values, the first plurality of the packed single precision floating point values including a first single precision floating point value in bits 31-0 of the source, a second single precision floating point value in bits 63-32 of the source, a third single precision floating point value, in bits 95-64 of the source, and a fourth single precision floating point value in bits 127-96 of the source; and
an execution resource coupled with the decode unit, the execution resource to store a packed result corresponding to the instruction in the destination indicated by the instruction, the packed result including a second plurality of packed single precision floating point values, the second plurality of the packed single precision floating point values including a fifth single precision floating point value in bits 31-0 of the packed result that is equal to the second single precision floating point value, a sixth single precision floating point value in bits 63-32 of the packed result that is equal to the second single precision floating point value, a seventh single precision floating point value in bits 95-64 of the packed result that is equal to the fourth single precision floating point value, and an eighth single precision floating point value in bits 127-96 of the packed result that is equal to the fourth single precision floating point value,
wherein the fifth and sixth single precision floating point values being equal to the second single precision floating point value is not explicitly specified by the instruction and,
wherein the instruction is to indicate an address of the source, and wherein the packed result is to be stored without the instruction indicating a second source having a same address as the source.