1. A semiconductor device comprising:
a plate of semiconductor layer;
an insulator layer containing a metal element on the plate of semiconductor layer and in contact with at least two adjoining faces of the plate of semiconductor layer, a thickness of the insulator layer being larger in the vicinity of a boundary line at a corner between the two adjoining faces of the plate of semiconductor layer than in a region other than the vicinity of the boundary line; and
a band of conductor layer facing a middle portion of the plate of semiconductor layer via the insulator layer.
2. The semiconductor device according to claim 1, further comprising:
a pair of conductive regions in the plate of semiconductor layer and on the respective sides of the middle portion of the plate of semiconductor layer, the conductive regions each including a region overlapping with the band of conductor layer.
3. The semiconductor device according to claim 1, wherein the insulator layer comprises at least two stacked layers on both of the at least two adjoining faces of the plate of semiconductor layer in the vicinity of the boundary line such that the at least two stacked layers are continuously formed in the vicinity of the boundary line, the at least two stacked layers including a layer having the smallest permittivity covering the two adjoining faces, and the thickness of the layer having the smallest permittivity is larger in the vicinity of the boundary line than in a region other than the vicinity of the boundary line.
4. The semiconductor device according to claim 3, wherein a layer having the largest permittivity in the stacked layers exists closer to the semiconductor layer than the layer having the smallest permittivity.
5. The semiconductor device according to claim 1, wherein the insulator layer comprises at least three stacked layers in the vicinity of the boundary line,
the at least three stacked layers including two layers having the smallest permittivity and a third layer therebetween, and
a thickness of at least one of the two layers having the smallest permittivity is larger in the vicinity of the boundary line than in a region other than the vicinity of the boundary line.
6. The semiconductor device according to claim 1, wherein a portion of the boundary line of the semiconductor layer is rounded.
7. The semiconductor device according to claim 1, wherein the metal element is one selected from the group consisting of Hf, Zr, Ti, Sc, Y, Ta, Al, La, Ce, and Pr.
8. The semiconductor device according to claim 7, wherein the insulator layer is either one of a first compound including the metal element and oxygen, or a second compound including the first compound and a silicon oxide.
9. The semiconductor device according to claim 1, wherein the insulator layer further contains nitrogen.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A wiring board with a built-in component, comprising:
an insulating board having an upper surface;
a first wiring pattern provided on the upper surface of the insulating board;
a plurality of electrodes provided on the upper surface of the insulating board;
a solder resist provided on the upper surface of the insulating board and surrounding the plurality of electrodes;
a plurality of solders provided on the plurality of electrodes, respectively;
an electronic component joined to the plurality of electrodes with the plurality of solders;
a sealing resin provided between the insulating board and the electronic component and entirely covering the plurality of solders and the solder resist;
a component-fixing layer provided on the upper surface of the insulating board and the first wiring pattern, the component-fixing layer entirely covering the electronic component and the sealing resin layer, the component-fixing layer having an insulating property;
a second wiring pattern provided on the component-fixing layer; and
an interlayer wiring connecting the first wiring pattern to the second wiring pattern.
2. A method for manufacturing a wiring board with a built-in component, comprising:
preparing a core layer which includes
an insulating board having an upper surface,
a first wiring pattern provided on the upper surface of the insulating board,
an electrode provided on the upper surface of the insulating board, and
a solder resist provided on the upper surface of the insulating board and surrounding the plurality of electrodes;
providing an electronic component having a solder bump;
placing the electronic component on the core layer such that the solder bump is placed on the electrode;
forming a solder joining the electronic component to the electrode by melting and solidifying the solder bump;
forming a sealing resin entirely covering the solder and the solder resist at a gap between the electronic component and the core layer;
after said forming the sealing resin, roughening an upper surface of the first wiring pattern;
providing a prepreg covering the electronic component and the roughened upper surface of the first wiring pattern;
forming a layered structure by providing a metal foil on an upper surface of the prepreg;
forming, by heating the layered structure, a component-fixing layer in which the prepreg fixes the core layer, the electronic component, and the metal foil; and
forming an interlayer wiring connecting the first wiring pattern to the metal foil.
3. The method according to claim 2, wherein the solder resist prevents the molten solder bump from flowing to an outside of the solder resist.
4. The method according to claim 2, further comprising:
applying a flux on the electrode or the solder bump before said placing the electronic component on the core layer; and
cleaning the solder, wherein
said forming the solder comprises forming the solder such that at least a part of the applied flux remains around the solder, and
said cleaning the solder comprises removing at least the part of the remaining flux.
5. The method according to claim 4, wherein: said forming the sealing resin comprises, after said cleaning the solder, putting and curing resin material between the electronic component and the core layer.
6. The method according to claim 2, wherein
said forming the sealing resin comprises, before said placing the electronic component on the core layer, supplying resin material onto the upper surface of the insulating board, the electrode, and the solder resist, and
said placing the electronic component on the core layer comprises placing the electronic component on the core layer such that the solder bump is placed on the electrode through the applied resin material.
7. The method according to claim 6, wherein: the resin material contains activator for removing an oxide film on the solder.
8. The method according to claim 2, further comprising
before said placing the electronic component on the core layer, applying first resin material on the solder bump, wherein
said placing the electronic component on the core layer comprises placing the electronic component on the core layer such that the solder bump is placed on the electrode through the coated resin material.
9. The method according to claim 8, wherein the first resin material contains activator for removing an oxide film on the solder.
10. The method according to claim 8, wherein said forming the sealing resin comprises, after said placing the electronic component on the core layer, putting and curing a second resin material between the electronic component and the core layer.
11. The method according to claim 2, wherein
the prepreg includes a second prepreg having an opening therein and a second prepreg having a board shape,
said providing the prepreg comprises placing the first prepreg on the roughened upper surface of the first wiring pattern such that the electronic component is positioned in the opening of the first prepreg, and
said forming the layered structure comprises:
providing a wiring layer including the second prepreg and the metal foil adhered onto an upper surface of the second prepreg; and
placing the wiring layer on the first prepreg such that the second prepreg is positioned on the first prepreg.
12. The method according to claim 2, wherein said roughening the upper surface of the first wiring pattern comprises roughening the upper surface of the first wiring pattern by oxidizing the upper surface of the first wiring pattern.
13. The method according to claim 2, further comprising
forming a second wiring pattern by patterning the metal foil.